21285-AB

Manufacturer Part Number21285-AB
DescriptionMicroprocessor, 21285 Core Logic For SA-110 Microprocessor
ManufacturerIntel Corporation
21285-AB datasheet
 


Specifications of 21285-AB

CaseBGADc99+/00+
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Functional Units
regardless of the value of the end-of-chain bit, and that this value can be 0 if the PCI
address of the transfer has 0 for its upper 32 bits.
— The address of the next descriptor (if any) is the address of the current descriptor plus 16.
This gives DMA control software the flexibility to provide PCI addresses anywhere in 64-bit
PCI memory space, as well as the ability to locate descriptors anywhere in local memory,
except for one limitation: when a descriptor has specified the upper 32-bit PCI address, the
next descriptor must be located contiguous in memory (that is, an address that is 16 greater
than the descriptor just fetched.
When the first descriptor is in the DMA channel registers, the channel DAC Address register
must be initialized (if a nonzero value is required,) and the D4 mode bit (bit [31] of the
SDRAM Address register) must be written to 0.
2. The SA-110 writes the address of the first descriptor into the DMA channel n descriptor
pointer register. As an alternative, the SA-110 can write the values of the parameters of the
first (or only) descriptor directly into the registers. If there is only one descriptor, the end of
chain bit [31] in the DMA channel n byte count register must be set, and the value of the DMA
channel n descriptor pointer register is a don’t care; otherwise, it must be the address of the
next descriptor.
3. The SA-110 writes the DMA channel n control register with other miscellaneous parameters,
and sets the channel enable bit. If the descriptor was written into the registers in step 2, the
channel initial descriptor in register bit [4] in the DMA channel n control register must also be
set.
4. If the channel initial descriptor in register bit [4] is clear, the channel reads the descriptor block
into the channel control, channel PCI address, channel SDRAM address, and channel
descriptor pointer registers.
5. The channel transfers the data until the byte count is exhausted, and then sets the channel
transfer done bit [2] in the DMA channel n control register.
6. If the end of chain bit [31] in the DMA channel n byte count register (which is in bit [31] of the
first word of the descriptor) is clear, the channel reads the next descriptor and transfers the
data. If it is set, the channel sets the chain done bit [7] in the DMA channel n control register
and then stops.
The channel initial descriptor in register bit [4] in the DMA channel n control register is useful for
nonchained transfers. It allows operation of the channel without the need to set up a list in
SDRAM.
There is no restriction on byte alignment of the source address or the destination address. DMA
reads are always unmasked reads (all byte enables asserted), either from SDRAM or PCI. For
PCI-to-SDRAM transfers, the PCI command is memory read, memory read line, or memory read
multiple according to the PCI read type field bits [6:5] in the DMA channel n control register.
After each read, the byte count is decremented by the number of bytes read, and the source address
is incremented.
After each write, the destination address is incremented by the number of bytes written. On the
initial write, some low-order bytes can be masked based on the low two bits of the destination
address as described in
that it is Dword aligned.
6-4
Table
6-1. After the first write, the destination address is incremented so
21285 Core Logic for SA-110 Datasheet