21285-AB

Manufacturer Part Number21285-AB
DescriptionMicroprocessor, 21285 Core Logic For SA-110 Microprocessor
ManufacturerIntel Corporation
21285-AB datasheet
 

Specifications of 21285-AB

CaseBGADc99+/00+
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Page 77/159:

DMA Channel Write

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Table 6-1. DMA Channel Write
a
Initial Destination
Address [1:0]
00
01
10
11
a.
Destination is SDRAM for PCI-to-SDRAM transfers, and PCI for SDRAM-to-PCI transfers.
In
Table
6-2, on the final write, some of the high-order bytes can be masked depending on the byte
count and the initial destination address.
Table 6-2. Final Write
Byte Count DIV 4
Remainder
0
1
2
3
a.
Destination is SDRAM for PCI-to-SDRAM transfers, and PCI for SDRAM-to-PCI transfers.
The 21285 may need to realign the data depending on the initial source and destination addresses.
The data in each byte lane is rotated right or left by 0, 1, 2, or 3 byte lanes as described in
Table
6-3. Data is packed into Dwords before being written to the destination.
Table 6-3. Aligning Byte Data
b
Initial Source
Address [1:0]
00
01
10
11
a.
Destination is SDRAM for PCI-to-SDRAM transfers, and PCI for SDRAM-to-PCI transfers.
b.
Source means PCI for PCI-to-SDRAM transfers, and SDRAM for SDRAM-to-PCI transfers.
21285 Core Logic for SA-110 Datasheet
Initial Byte Enable
(Active High)
1111
1110
1100
1000
Final Byte Enable (Active High)
Initial Destination Address
00
01
1111
0001
0001
0011
0011
0111
0111
1111
Initial Destination
00
01
0
Left 1
Right 1
0
Right 2
Right 1
Right 3
Right 2
Functional Units
a
[1:0]
10
11
0011
0111
0111
1111
1111
0001
0001
0011
a
Address [1:0]
10
11
Left 2
Left 3
Left 1
Left 2
0
Left 1
Right 1
0
6-5