PEB2254HV1.4 Infineon Technologies AG, PEB2254HV1.4 Datasheet
PEB2254HV1.4
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PEB2254HV1.4 Summary of contents
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ICs for Communications Framing and Line Interface Component for PCM 30 and PCM 24 FALC54 PEB 2254 Version 1.3 Data Sheet 11.96 T2254-XV13-D1-7600 ...
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PEB 2254 Revision History: Previous Version: Page Page (in previous Version) (in current Version) – 52, 53, 108 – 42, 108 – 102, 251 69, 70, 218, 219 70, 71, 216, 217 – 87, 236 – 113, 261 – 55, ...
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Table of Contents FALC54 in PCM 30 Mode 1 General Features ...
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Table of Contents FALC54 in PCM 24 Mode 4 General Features ...
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Table of Contents 7.6.1 Timing of Dual Rail and Optical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 299 7.7 System ...
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Framing and Line Interface Component FALC54 FALC54 in PCM 30 Mode 1 General Features E1 Line Interface • Analog receive and transmit circuitry for E1 signals • Data and clock recovery using an integrated digital phase locked loop • Low ...
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Performance monitoring 16 bit counter for CRC-, framing errors, code violations, Error monitoring via E bit and SA6 bit • Insertion and extraction of alarms (AIS, Remote (Yellow) Alarm, AUXP …) • IDLE code insertion for selectable channels • ...
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Pin Configuration of FALC (top view) Figure 1 Note: All unused input pins including pin 80 have to be connected to a defined level. Semiconductor Group P-MQFP-80-1 8 PEB 2254 General Features E1 11.96 ...
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Pin Definitions and Functions Pin No. Symbol 42 … … … … … … D11 25 … 22 D12 … D15 49 ALE Semiconductor Group Input (I) Function Output ...
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Pin Definitions and Function (cont’d) Pin No. Symbol 50 RD/DS 51 WR/ Semiconductor Group Input (I) Function Output (O) I Read Enable (Siemens/Intel bus mode) This signal indicates a read operation. When the FALC54 is selected via CS ...
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Pin Definitions and Function (cont’d) Pin No. Symbol 54 RES 53 BHE/BLE 11 DBW Semiconductor Group Input (I) Function Output (O) I Reset A high signal on this pin forces the FALC54 into reset state. During Reset the FALC54 needs ...
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Pin Definitions and Function (cont’d) Pin No. Symbol 56 INT DDR 2 RL1 RDIP ROID Semiconductor Group Input (I) Function Output (O) O/oD Interrupt Request INT serves as general interrupt request which may include all interrupt ...
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Pin Definitions and Function (cont’d) Pin No. Symbol 3 REFR 4 RL2 RDIN RCLKI 5 V SSR 6 XTAL2 7 XTAL1 9 XTAL4 10 XTAL3 Semiconductor Group Input (I) Function Output (O) O Reference Resistance of 12K 1 % connected ...
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Pin Definitions and Function (cont’d) Pin No. Symbol 13 XL2 XDON 14 V SSX Semiconductor Group Input (I) Function Output (O) O Transmit Line 2 Analog output for the external transformer. Selected if LIM1.DRS = 0. After Reset this pin ...
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Pin Definitions and Function (cont’d) Pin No. Symbol 15 XL1 XDOP XOID 17 XL1M Semiconductor Group Input (I) Function Output (O) O Transmit Line 1 Analog output for the external transformer. Selected if LIM1.DRS = 0. After Reset this pin ...
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Pin Definitions and Function (cont’d) Pin No. Symbol 12 XL2M 16 V DDX 79 XCLK FSC 80 N.C. 66 FSC 75 CLK16M 76 CLK12M 77 CLK8M 78 CLKX Semiconductor Group Input (I) Function Output (O) I Transmit Line 2 Monitor ...
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Pin Definitions and Function (cont’d) Pin No. Symbol Input (I) Output (O) 60 SYNC I 72 RCLK O 57 RDO O 71 RFSP O Semiconductor Group Function Clock Synchronization If a clock is detected at the SYNC pin the FALC54 ...
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Pin Definitions and Function (cont’d) Pin No. Symbol Input (I) Output (O) 70 DLR O 68 XMFB O 59 XSIGM O 65 SYPR I 64 SYPX I 63 SCLKR I 62 SCLKX I Semiconductor Group Function Data Link Bit Receive ...
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Pin Definitions and Function (cont’d) Pin No. Symbol Input (I) Output (O) 55 XDI I 69 DLX O 58 RSIGM O 67 RMFB O Semiconductor Group Function Transmit Data In Transmit data received from the system internal highway with 4096 ...
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Pin Definitions and Function (cont’d) Pin No. Symbol 61 XMFS V 27, 37 26, 36 TDI 21 TDO 19 TMS 20 TCK Semiconductor Group Input (I) Function Output (O) I External Transmit Multiframe Synchronization ...
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Logic Symbol Figure 2 FALC54 Logic Symbol Semiconductor Group General Features E1 21 PEB 2254 11.96 ...
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Functional Block Diagram Figure 3 Functional Block Diagram PEB 2254 Semiconductor Group General Features E1 22 PEB 2254 11.96 ...
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System Integration The figures below show a multiple link application and a NT application. Figure 4 Multiple Link Application Semiconductor Group General Features E1 23 PEB 2254 11.96 ...
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Figure Application 1.6 Microprocessor Interface The communication between the CPU and the FALC54 is done via a set of directly accessible registers. The interface may be configured as Siemens/Intel or Motorola type with a selectable data bus ...
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Mixed Byte/Word Access to the FIFOs Reading from or writing to the internal FIFOs (RFIFO and XFIFO of each channel) can be done using a 8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode. Randomly mixed ...
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The assignment of registers with even/odd addresses to the data lines in case of 16-bit register access depends on the selected microprocessor interface mode: Siemens/Intel (Adr Motorola (Adr. n) Data Lines D15 n: even address Complete information ...
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Figure 6 FIFO Word Access (Intel Mode) Semiconductor Group General Features E1 27 PEB 2254 11.96 ...
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Figure 7 FIFO Word Access (Motorola Mode) Semiconductor Group General Features E1 28 PEB 2254 11.96 ...
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Interrupt Interface Special events in the FALC54 are indicated by means of a single interrupt output with programmable characteristics (open drain, push-pull; IPC register), which requests the CPU to read status information from the FALC transfer data from/to ...
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Masked Interrupts Visible in Status Registers The Global Interrupt Status register (GIS) indicates those interrupt status registers with active interrupt indications (GIS.ISR0-3). An additional mode can be selected via bit IPC.VIS. In this mode, masked interrupt status bits neither generate ...
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General Functions and Device Architecture E1 2.1 Functional Description E1 2.1.1 Receive Path Figure 9 Receive Clock System Receive Line Interface For data input, three different data types are supported: • Ternary coded signals received at multifunction ports RL1 ...
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Receive Clock and Data Recovery The analog received signal at port RL1/2 is equalized and then peak-detected to produce a digital signal. The digital received signal at port RDIP/N is directly forwarded to the DPLL. The receive clock and data ...
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Recommended Receiver Configuration Values Parameter Jitter free system clocks ( MHz and 8 kHz) are ...
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LOS alarm. Additional recovery conditions may be programmed by register LIM2. Jitter Attenuator Together with a PLL and a tunable crystal attenuation of received input jitter is done in ...
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Jitter Tolerance The FALC54 receiver’s tolerance to input jitter complies to ITU for CEPT application. Figure 12 shows the curves of different input jitter specifications stated above as well as the FALC54 performance. Figure 12 Jitter Tolerance Output Jitter In ...
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Clock Generation and Clock Modes The high performance integrated Clock Generator meets the recommendations of ITU-T G.735, G824 and I.431 in case of input jitter tolerance, jitter transfer characteristic and output jitter. The following table shows the clock modes with ...
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Figure 13 Transmit Clock System Framer/Synchronizer The following functions are performed: • Synchronization on pulse frame • Synchronization on multiframe • Error indication when synchronization is lost. In this case, AIS is automatically sent to the system side and Remote ...
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If programmed and applicable to the selected multiframe format, CRC checking of the incoming data stream is done by generating check bits for a CRC submultiframe according to the CRC 4 procedure (refer to ITU-T Rec. G704). These bits are ...
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Figure 14 The Receive Elastic Store as Circularly Organized Memory Additionally the receive elastic store can be switched to one frame length (LOOP.SFM). This feature is useful for master-slave applications to reduce the delay between line interface and system interface. ...
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Receive Signaling Controller The receive signaling controller can be programmed to operate in various signaling modes. The FALC54 will perform the following signaling and data link methods: • Message Oriented Signaling also called Common Channel Signaling CCS • Channel Associated ...
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Latching of data is controlled by the System Clock (SCLKX) and the Synchronous Pulse (SYPX) in conjunction with the programmed offset values for the Transmit Time-slot/Clock-slot Counters. The clock for the transmit data is internal derived directly from the system ...
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Transmit Line Interface The analog transmitter transforms the unipolar bit stream to ternary (alternate bipolar) return to zero signals of the appropriate programmable shape. The unipolar data is provided by the digital transmitter. Figure 15 Transmitter Configuration Recommended Transmitter Configuration ...
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Transmit Line Monitor The transmit line monitor compares the transmit line pulses on XL1 and XL2 with the transmit input signals received on pins XL1M and XL2M. The monitor detects faults on the primary side of the transformer and protects ...
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Transparency in transmit direction can be achieved by activating the time-slot 0 transparent mode (bit XSP.TT0 or TSWM.7-0). If XSP.TT0 = 1 all internal information of the FALC54 (framing, CRC, Sa/Si bit signaling, remote alarm) will be ignored. With register ...
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Operating Modes E1 General Bit: FMR1.PMOD = 0 PCM line bit rate : 2048 kbit/s Single frame length : 256 bit, No. 1 … 256 Framing frequency : 8 kHz HDLC controller : Organization : 32 time-slots, No. 0 ...
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The next pages give a general description of the assigned framing formats. After RESET, the FALC54 is switched into doubleframe format automatically. Time-slot 0 is reserved for frame alignment word and service information. Switching between the two applicable framing formats ...
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Signaling • CCS For Common Channel Signaling the use of time-slot 16 is recommended. The use of CCS is allowed with both the doubleframe and the CRC-multiframe format. • CAS-CC For Channel Associated Signaling the use of time-slot 16 is ...
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For transmit direction, contents of time-slot 0 are additionally determined by the selected transparent mode: Mode Framing – (int. generated) XSP.TT0 via pin XDI TSWM.TSIF (int. generated) TSWM.TSIS (int. generated) TSWM.TRA (int. generated) TSWM.TSA4-8 (int. generated) 1) Additionally, automatic transmission ...
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A-Bit Access If the FALC54 detects a remote alarm indication in the received data stream the interrupt status bit ISR2.RA will be set. By setting FMR2.AXRA the FALC54 automatically transmit the remote alarm bit = 1 in the outgoing data ...
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Table 6 CRC-Multiframe Structure Sub- Multiframe Multiframe Spare bits for international use. Access to received information via bits RSP.RS13 and RSP.RS15. Transmission is enabled via bits XSP.XS13 and XSP.XS15. Additionally, automatic transmission for submultiframe error indication is ...
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For transmit direction, contents of time-slot 0 are additionally determined by the selected transparent mode: Mode Framing + CRC A Bit – (int. generated) XSP.TT0 via pin XDI TSWM.TSIF (int. generated) TSWM.TSIS (int. generated) TSWM.TRA (int. generated) TSWM.TSA4–8 (int. generated) ...
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The multiframe synchronous state is established after detecting two correct multiframe alignment signals at an interval of n alignment flag FRS0.LMFA will be reset. Additionally an interrupt status multiframe alignment recovery bit ISR2.MFAR is generated with the falling edge of ...
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During the parallel search all receiver functions are based on the primary frame alignment signal, like framing errors, Sa-, Si-, A-bits …). All subsequent multiframe searches are associated with each basic framing sequence found during the parallel ...
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S - Bit Access a Due to signaling procedures using the five S CRC multiframe structure, three possibilities of access via the microprocessor are implemented. • The standard procedure allows reading/writing the S further support. The S • The advanced ...
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SA6-Bit Detection according to ETS 300233 Four consecutive received SA6-bits are checked on the by ETS 300233 defined SA6-bit combinations. The FALC54 will detect following fixed SA6-bit combinations: SA61,SA62,SA63,SA64 = 1000; 1010; 1100; 1110; 1111. All other possible 4 bit ...
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E-Bit Access Due to signaling requirements, the E bits of frame 13 and frame 15 of the CRC multiframe can be used to indicate received errored submultiframes: Submultiframe I status Submultiframe II status no CRC error: : CRC error: : ...
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Test Functions There are two types of monitoring/testing functions: • Active tests which partly degrade the functionality (e.g. Payload Loop, Remote Loop, Local Loop, test loop for a single channel). • Diagnostics, during which the device is not operational ...
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Payload Loop Back To perform an effective circuit test a payload loop is implemented. The payload loop back (FMR2.PLB) will loop the data stream from the receiver section back to transmitter section. The looped data will pass the complete receiver ...
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Local Loop The local loopback mode, selected by LIM0. disconnects the receive lines RL1/2 or RDIP/RDIN from the receiver. Instead of the signals coming from the line the data provided by system interface are routed through the analog ...
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Remote Loop In the remote loopback mode the clock and data recovered from the line inputs RL1/2 or RDIP/RDIN are routed back to the line outputs XL1/2 or XDOP/XDON via the analog or digital transmitter normal mode they ...
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Alarm Simulation Alarm simulation does not affect the normal operation of the device, i.e. all channels remain available for transmission. However, possible ‘real’ alarm conditions are not reported to the processor or to the remote end when the device is ...
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Signaling Controller Operating Modes The HDLC controller can be programmed to operate in various modes, which are different in the treatment of the HDLC frame in receive direction. Thus, the receive data flow and the address recognition features can ...
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Transparent Mode 1 (MODE.MDS2-0=101) Characteristics: address recognition, FLAG - and CRC generation/check, bit-stuffing Only the high byte of a 2-byte address field will be compared with registers RAH1/2. The whole frame excluding the first address byte will be stored in ...
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Receive Data Flow The following figure gives an overview of the management of the received HDLC frames in the different operating modes. Figure 23 Receive Data Flow of FALC Semiconductor Group General Functions and Device Architecture E1 64 PEB 2254 ...
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Transmit Data Flow The frames can be transmitted as shown below. Figure 24 Transmit Data Flow of FALC54 Transmitting a HDLC frame via register CMDR.XTF, the address, the control fields and the data field have to be entered in the ...
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Special Functions Shared Flags The closing Flag of a previously transmitted frame simultaneously becomes the opening Flag of the following frame if there is one to be transmitted. The Shared Flag feature is enabled by setting bit SFLG in ...
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Cyclic Transmission (fully transparent) If the extended transparent mode is selected, the FALC54 supports the continuous transmission of the contents of the transmit FIFO. After having written bytes to XFIFO, the command XREP.XTF via the CMDR register ...
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Time-Slot Assigner The FALC54 offers the flexibility to extract or insert data during certain time-slots which are defined via registers RTR1-4 and TTR1-4. Any combination of time-slots can be programmed independent for the receive and transmit direction. Table 7 ...
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S bit Access a The FALC54 supports the S ways. The access via registers RSW/XSW, the access via registers R/XSA8-4, capable of storing the information for a complete multiframe, and the most effective one is the access via the ...
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Interface to System Internal Highway Figure 25 Data on RDO Semiconductor Group General Functions and Device Architecture E1 70 PEB 2254 11.96 ...
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Figure 26 Data on XDI Semiconductor Group General Functions and Device Architecture E1 71 PEB 2254 11.96 ...
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Figure 27 Supporting Signals for CCS/CAS-CC Applications Figure 28 2-Mbyte/s Interface Mode Semiconductor Group General Functions and Device Architecture E1 72 PEB 2254 11.96 ...
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Figure 29 4-Mbyte System Interface Mode Semiconductor Group General Functions and Device Architecture E1 73 PEB 2254 11.96 ...
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Operational Description E1 Reset The FALC54 is forced to the reset state if a high signal is input at port RES for a minimum period During RESET, all output stages except CLK16M, CLK12M, CLK8M, CLKX, FSC, ...
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Table 8 Initial Values after RESET (cont’d) Register Reset Value Meaning MODE 00 H PRE 00 H RAH1 RAL1 Operational Phase The FALC54 is programmable via a microprocessor interface which enables access ...
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Table 9 Initialization Parameters Basic Set Up Mode Select Specification of Line interface and clock generation Line interface coding Loss of Signal detection / recovery conditions System interface mode Transmit offset counters Receive offset counters AIS to system interface Operational ...
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HDLC Data Transmission In transmit direction 2x32 byte FIFO buffers are provided. After checking the XFIFO status by polling the bit SIS.XFW or after an interrupt ISR1.XPR (Transmit Pool Ready bytes may be entered by the CPU ...
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Figure 30 Interrupt Driven Data Transmission (flow diagram) The activities at both serial and CPU interface during frame transmission (supposed frame length = 70 bytes) is shown in figure 31. Figure 31 Interrupt Driven Transmission Sequence Example Semiconductor Group Operational ...
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Data Reception Also 2x32 byte FIFO buffers are provided in receive direction. There are different interrupt indications concerned with the reception of data: HDLC RPF (Receive Pool Full) interrupt, indicating that a 32-byte-block of data can be read from RFIFO ...
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Detailed Register Description E1 3.1.1 Control Register Description Table 10 Control Register Address Arrangement Address Register Type 00 XFIFO W 01 XFIFO W 02 CMDR W 03 MODE R/W 04 RAH1 R/W 05 RAH2 R/W 06 RAL1 R/W 07 ...
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Table 10 Control Register Address Arrangement (cont’d) Address Register Type 1B FMR1 R/W 1C FMR2 R/W 1D LOOP R/W 1E XSW R/W 1F XSP R/W 20 XC0 R/W 21 XC1 R/W 22 RC0 R/W 23 RC1 R/W 24 XPM0 R/W ...
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Table 10 Control Register Address Arrangement (cont’d) Address Register Type 60 DEC W 62 TEST W 70 XS1 W 71 XS2 W 72 XS3 W 73 XS4 W 74 XS5 W 75 XS6 W 76 XS7 W 77 XS8 W ...
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Transmit FIFO (WRITE) XFIFO 7 XFIFO XF7 bytes/16 words of received data can be read from the RFIFO following a RPF or a RME interrupt. Writing data to XFIFO can be done in 8-bit (byte) or 16-bit ...
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XRES… Transmitter Reset The transmit framer and transmit line interface excluding the system clock generator and the pulse shaper will be reset. However the contents of the control registers will not be deleted. XHF… Transmit HDLC Frame After having written ...
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Mode Register (Read/Write) Value after RESET MODE MDS2 MDS1 MDS2-0… Mode Select The operating mode of the HDLC controller is selected. 000… Reserved 001… Reserved 010… 1 byte address comparison mode (RAL1,2) 011… 2 byte address comparison ...
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Receive Address Byte High Register 2 (Read/Write) Value after RESET RAH2 RAH2… Value of Second Individual High Address Byte Receive Address Byte Low Register 1 (Read/Write) Value after RESET RAL1 RAL1… Value of First ...
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VIS… Masked Interrupts Visible 0… Masked interrupt status bits are not visible. 1… Masked interrupt status bits are visible. SCI… Status Change Interrupt 0… Interrupts will be generated either on coming or going of the internal interrupt source. 1… The ...
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CASM… CAS Synchronization Mode Determines the synchronization mode of the channel associated signaling multiframe alignment. 0… Synchronization is done in accordance to ITU-T G. 732 1… Synchronization is established when two consecutively correct multiframe alignment pattern are found. EITS… Enable ...
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RFT1 Common Configuration Register 3 (READ/WRITE) Value after RESET CCR3 PRE1 PRE0 Note: Unused bits have to be set to logical ‘0’. PRE1, PRE0… Number of Preamble Repetition If Preamble transmission is initiated, ...
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RADD… Receive Address Pushed to RFIFO If this bit is set to ‘1’, the received HDLC address information ( bytes, depending on the address mode selected via MODE.MDS0) is pushed to RFIFO. This function is applicable in non-auto ...
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Receive Timeslot Register 1-4 (Read/Write) Value after RESET RTR1 TS0 TS1 RTR2 TS8 TS9 RTR3 TS16 TS17 RTR4 TS24 TS25 TS0…TS31… Timeslot Register These bits define the received channels (time-slots extracted. Additionally this ...
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Transmit Timeslot Register 1-4 (Read/Write) Value after RESET TTR1 TS0 TS1 TTR2 TS8 TS9 TTR3 TS16 TS17 TTR4 TS24 TS25 TS0…TS31… Transmit Timeslot Register These bits define the transmit channels (time-slots inserted. Additionally ...
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Interrupt Mask Register 0 ... 4 Value after RESET IMR0 RME RFS IMR1 RDO IMR2 FAR LFA IMR3 ES SEC IMR4 LFA FER IMR0...IMR4... Interrupt Mask Register Each interrupt source can generate an interrupt signal ...
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RC1... RC0… Receive Code Serial code receiver is different programmable from the transmitter. 00... NRZ (optical interface) 01... CMI (1T2B+HDB3), (optical interface) 10... AMI (ternary or digital dual rail interface) 11... HDB3 Code (ternary or digital dual rail interface) EXTD… ...
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SIM… Alarm Simulation 0… Normal operation. 1… Initiates internal error simulation of AIS, loss of signal, loss of synchronization, auxiliary pattern indication, slip, framing errors, CRC errors, and code violations. The error counters FEC, CVC, CEC1 will be incremented. Framer ...
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PMOD… PCM Mode For E1 application this bit must be set low. 0... PCM30 mode. 1... PCM24 mode. XFS… Transmit Framing Select Selection of the transmit framing format could be done independent of the receive framing format. 0… Doubleframe format ...
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Framer Mode Register 2 (Read/Write) Value after RESET FMR2 RFS1 RFS0 RFS1... RFS0... Receive Framing Select 00 ... Doubleframe format 01 ... Doubleframe format 10 ... CRC4 Multiframe format 11 ... CRC4 Multiframe format with modified CRC4 ...
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AXRA… Automatic Transmit Remote Alarm 0 ... Normal operation 1 ... The Remote Alarm bit will be automatically set in the outgoing data stream if the receiver is in asynchronous state (FRS0.LFA bit is set). In synchronous state the remote ...
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Transmit Service Word Pulseframe (Read/Write) Value after RESET XSW XSIS XSIS… Spare Bit For International Use First bit of the service word. Only significant in doubleframe format. If not used, this bit should be fixed to ‘1’. ...
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CASEN… Channel Associated Signaling Enable 0… Normal operation. 1… A one in this bit position will cause the transmitter to send the CAS information stored in the XS1-16 registers in the corresponding time slots. TT0… Time-Slot 0 Transparent Mode 0… ...
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XSIF… Transmit Spare Bit For International Use (FAS Word) First bit in the FAS word. Only significant in doubleframe format. If not used, this bit should be fixed to ‘1’. If one of the time-slot 0 transparent modes is enabled ...
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XCO2…XCO0… Transmit Clock Slot Offset Initial value loaded into the transmit bit counter at the trigger edge of SCLKX when the synchronous pulse at port SYPX is active (see figure 26). Transmit Control 1 (Read/Write) Value after RESET ...
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SICS… System Interface Channel Select Only applicable if bit FMR1.IMOD (4 MHz system interface) is set. 0… Received data is output on port RDO in the first channel phase. Data in the second channel phase is tri-stated. Data on pin ...
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Errors in service words have no influence when in synchronous state. However, they are used for the resynchronization procedure. ASY4… Select Loss of Sync Condition 0… Standard operation. Three consecutive incorrect FAS words or three consecutive incorrect service words ...
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Changing the LSB of each subpulse in registers XPM2-0 will change the amplitude of the differential voltage on XL1/2 by approximately 110 mV. Example: 120 interface and wired as shown in figure 15. XPM04-00: 1D XPM14-10: 1D XPM24-20: 00 XPM34-30: ...
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Transparent Service Word Mask (Read/Write) Value after RESET TSWM TSIS TSIF TSWM7…TSWM0…Transparent Service Word Mask TSIS… Transparent Si Bit in Service Word 0… The SI Bit will be generated internally. 1… The SI Bit in the service ...
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Idle Channel Code Register (Read/Write) Value after RESET IDLE IDL7 IDL7…IDL0… Idle Channel Code If channel loop back is enabled by programming LOOP.ECLB=1, the contents of the assigned outgoing channel at ports XL1/XL2 resp. XDOP/XDON is set ...
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Framer Mode Register 3 (Read/Write) Value after RESET FMR3 CMI… Select CMI Precoding Only valid if CMI code (FMR0.XC1/0=01) is selected. This bit defines the CMI precoding and influences only the transmit data and not the receive ...
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Idle Channel Register (Read/Write) Value after RESET ICB1 IC0 IC1 ICB2 IC8 IC9 ICB3 IC16 IC17 ICB4 IC24 IC25 IC1…IC32… Idle Channel Selection Bits These bits define the channels (time-slots) of the outgoing PCM frame ...
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XDOS… Transmit Data Out Sense 0… Output signals XDOP/XDON are active low. Output XOID is active high (normal operation). 1… Output signals XDOP/XDON are active high. Output XOID is active low. Note: If CMI coding is selected (FMR0.XC1/0=01) this bit ...
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MAS… Master Mode 0… Slave mode 1… Master mode on. If this bit is set and the SYNC pin is connected to internal DCO’s of the jitter attenuator are centered and the system clocks which are output via CLK8M/CLKX are ...
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JATT…RL... Transmit Jitter Attenuator / Remote Loop 00 ... Normal operation. The transmit jitter attenuator is disabled. Transmit data will bypass the buffer. 01 ... Remote Loop active without transmit jitter attenuator enabled. Transmit data will bypass the buffer. 10 ...
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Pulse Count Recovery (Read/Write) Value after RESET PCR PCR7 PCR7…PCR0… Pulse Count Recovery A LOS alarm will be cleared if a pulse density is detected in the received bit stream. The number of pulses M which must ...
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Disable Error Counter (Write) Value after RESET DEC DCEC3… Disable CRC Error Counter 3 Only valid if FMR1.ECM is reset. This bit has to be set before reading the CRC error counter 3. It will be automatically ...
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DFEC… Disable Framing Error Counter Only valid if FMR1.ECM is reset. This bit has to be set before reading the framing error counter. It will be automatically reset if the corresponding error counter high byte has been read. With the ...
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Transmit CAS Register (Write) Value after RESET: not defined 7 XS1 0 0 XS2 A1 B1 XS3 A2 B2 XS4 A3 B3 XS5 A4 B4 XS6 A5 B5 XS7 A6 B6 XS8 A7 B7 XS9 A8 B8 XS10 A9 B9 ...
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Status Register Address Arrangement Address Write Type 00/01 RFIFO R 4C FRS0 R 4D FRS1 R 4E RSW R 4F RSP R 50 FECL R 51 FECH R 52 CVCL R 53 CVCH R 54 CEC1L R 55 CEC1H ...
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E1: Status Register Address Arrangement (cont’d) Address Write Type 66 RBCL R 67 RBCH R 68 ISR0 R 69 ISR1 R 6A ISR2 R 6B ISR3 GIS R 6F VSTR R 70 RS1 R 71 RS2 ...
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Receive FIFO (Read) RFIFO 7 RFIFO RF7 Reading data from RFIFO can be done in an 8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode. The LSB is received first from the serial interface. The size ...
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Recovery: Analog interface: The bit will be reset when the incoming signal has transitions with signal levels greater than the programmed receive input level (LIM1.RIL2-0) for at least M pulse periods defined by register PCR in the PCD time interval. ...
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The following conditions have to be detected to regain synchronous state: – The presence of the correct FAS word in frame n. – The presence of the correct service word (bit frame – ...
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NMF… No Multiframe Alignment Found This bit is only valid if the CRC4 interworking is selected (FMR2.RFS1/0 = 11). Set if the multiframe pattern could not be detected in a time interval of 400 msec after the framer has reached ...
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TS16AIS… Receive Timeslot 16 Alarm Indication Signal The detection of the alarm indication signal in timeslot 16 is according to ITU-T G.775. This bit is set if the incoming TS16 contains less than 4 zeros in each of two consecutive ...
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Receive Service Word Pulseframe (Read) 7 RSW RSI 1 RSI… Receive Spare Bit for International Use First bit of the received service word fixed to one if CRC- multiframe mode is enabled. RRA… Receive Remote Alarm Equivalent to ...
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RSIF… Receive Spare Bit for International Use (FAS Word) First bit in FAS-word. Used only in doubleframe format, otherwise fixed to ‘1’. RS13… Receive Spare Bit (Frame 13, CRC Multiframe) First bit in service word of frame 13. Significant only ...
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Code Violation Counter (Read) 7 CVCL CV7 7 CVCH CV15 CV15…CV0… Code Violations No function if NRZ code has been enabled. If the HDB3 or the CMI code is selected, the 16-bit counter will be incremented when violations of the ...
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CRC Error Counter 1 (Read) 7 CEC1L CR7 7 CEC1H CR15 CR15…CR0… CRC Errors No function if doubleframe format is selected. In CRC-multiframe mode, the 16-bit counter will be incremented when a CRC-submultiframe has been received with a CRC error. ...
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E Bit Error Counter (Read) 7 EBCL EB7 7 EBCH EB15 EB15…EB0… E-Bit Errors If doubleframe format is selected, FEBEH/L has no function. If CRC- multiframe mode is enabled, FEBEH/L works as submultiframe error indication counter (16 bits) which counts ...
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CRC Error Counter 2 (Read) 7 CEC2L CC7 7 CEC2H CC15 CC15…CC0… CRC Error Counter (Reported from TE via Sa6 -Bit) If doubleframe format is selected, CEC2H/L has no function. If CRC- multiframe mode is enabled, CEC2H/L works as SA6 ...
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CRC Error Counter 3 (Read) 7 CEC3L CE7 7 CEC3H CE15 CE15…CE0… CRC Error Counter (detected at T Ref. Point via Sa6 -Bit) If doubleframe format is selected, CEC3H/L has no function. If CRC- multiframe mode is enabled, CEC3H/L works ...
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Receive Sa4-Bit Register (Read) 7 RSA4 RS47 RS47…RS40… Receive Sa4-Bit Data (Y-Bits) This register contains the information of the eight SA4 bits of the previously received CRC multiframe (bit-slot 4 of every service word). RS40 is received in frame 1, ...
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Receive Sa7-Bit Register (Read) 7 RSA7 RS77 RS77…RS70… Receive Sa7-Bit Data (Y-Bits) This register contains the information of the eight SA7 bits of the previously received CRC multiframe (bit-slot 7 of every service word). RS70 is received in frame 1, ...
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A valid SA6-bit combination must occur three times in a row. The corresponding status bit in this register will be set. Even if the detected status will be active for a short time the status bit remains active until this ...
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Signaling Status Register (Read) 7 SIS XDOV XFW XDOV… Transmit Data Overflow More than 32 bytes have been written to the XFIFO. This bit is reset by: – a transmitter reset command XRES – or when all bytes in the ...
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Receive Signaling Status Register (Read) 7 RSIS VFR RDO RSIS relates to the last received HDLC frame copied into RFIFO when end-of-frame is recognized (last byte of each stored frame). VFR… Valid Frame Determines whether a valid frame ...
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HA1, HA0… High Byte Address Compare Significant only if 2-byte address mode has been selected. In operating modes which provide high byte address recognition, the FALC54 compares the high byte of a 2-byte address with the contents of two individually ...
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Received Byte Count High (Read) Value after RESET: 000 xxxxx 7 RBCH OV… Counter Overflow More than 4095 bytes received. RBC11 – RBC8…Receive Byte Count (most significant bits) Together with RBCL (bits RBC7…RBC0) indicate the length of the received frame. ...
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RFS… Receive Frame Start This is an early receiver interrupt activated after the start of a valid frame has been detected, i.e. after an address match (in operation modes providing address recognition), or after the opening flag (transparent mode 0) ...
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RPF… Receive Pool Full 32 bytes of a frame have arrived in the receive FIFO. The frame is not yet completely received. Interrupt Status Register 1 (Read) 7 ISR1 RDO All bits are reset when ISR1 is read. If bit ...
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XMB… Transmit Multiframe Begin This bit is set every 2 ms with the beginning of a transmitted multiframe related to the internal transmitter timing. Just before setting this bit registers XS1-16 are copied in the transmit shift registers. The registers ...
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MFAR… Multiframe Alignment Recovery Set when the framer has found two CRC-multiframes at an interval …) without a framing error. At the same time bit FRS0.LMFA is reset ...
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Interrupt Status Register 3 (Read) 7 ISR3 ES SEC All bits are reset when ISR3 is read. If bit IPC.VIS is set to ‘1’, interrupt statuses in ISR3 may be flagged although they are masked via register IMR3. However, these ...
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RA16… Remote Alarm TS 16 Status Change A change in the remote alarm bit in CAS multiframe alignment word is detected. API… Auxiliary Pattern Indication This bit is set if the auxiliary pattern is detected in the received bitstream and ...
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Receive CAS Register (Read) Value after RESET: not defined 7 RS1 0 0 RS2 A1 B1 RS3 A2 B2 RS4 A3 B3 RS5 A4 B4 RS6 A5 B5 RS7 A6 B6 RS8 A7 B7 RS9 A8 B8 RS10 A9 B9 ...
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Framing and Line Interface Component FALC54 FALC54 in PCM 24 Mode 4 General Features T1 Line Interface • Analog receive and transmit circuitry • Data and clock recovery using an integrated digital phase locked loop • Maximum line attenuation up ...
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Frame Aligner • Frame alignment/synthesis for 1544 kbit/s according to ITU-T G.704 • Meets newest ITU-T Rec's, ANSI T1 and AT&T Technical References • Programmable formats for PCM 24: 4-Frame Multiframe (F4), 12-Frame Multiframe (F12, D3/4), Extended Superframe (ESF), Remote ...
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MP Interface • 8/16 bit microprocessor bus interface (Intel or Motorola type) • All registers directly accessible (byte or word access) • Extended interrupt capabilities General • Boundary Scan Standard IEEE 1149.1 • Advanced CMOS technology • P-MQFP-80 Package The ...
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Pin Configuration of FALC (top view) Figure 33 Semiconductor Group P-MQFP-80-1 148 PEB 2254 General Features T1 11.96 ...
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Pin Definitions and Function Pin No. Symbol 42 … … … … … … D11 25 … 22 D12 … D15 49 ALE Note: All unused input pins including ...
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Pin Definitions and Function (cont’d) Pin No. Symbol Input (I) Output (O) 50 RD/ WR/ RES I Semiconductor Group Function Read Enable (Siemens/Intel bus mode) This signal indicates a read operation. When the ...
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Pin Definitions and Function (cont’d) Pin No. Symbol Input (I) Output (O) 53 BHE/BLE I 11 DBW I 56 INT O/ DDR Semiconductor Group Function Bus High Enable (Siemens/Intel bus mode) If 16-bit bus ...
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Pin Definitions and Function (cont’d) Pin No. Symbol Input (I) Output (O) 2 RL1 I RDIP I ROID I 3 REFR O Semiconductor Group Function Line Receiver 1 Analog Input from the external transformer. Selected if LIM1.DRS = 0. Receive ...
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Pin Definitions and Function (cont’d) Pin No. Symbol Input (I) Output (O) 4 RL2 I RDIN I RCLKI SSR 6 XTAL2 O 7 XTAL1 I 9 XTAL4 O 10 XTAL3 I Semiconductor Group Function Line Receiver ...
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Pin Definitions and Function (cont’d) Pin No. Symbol Input (I) Output (O) 13 XL2 O XDON SSX Semiconductor Group Function Transmit Line 2 Analog output for the external transformer. Selected if LIM1.DRS = 0. After Reset ...
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Pin Definitions and Function (cont’d) Pin No. Symbol Input (I) Output (O) 15 XL1 O XDOP O XOID O 17 XL1M I Semiconductor Group Function Transmit Line 1 Analog output for the external transformer. Selected if LIM1.DRS = 0. After ...
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Pin Definitions and Function (cont’d) Pin No. Symbol Input (I) Output (O) 12 XL2M I 16 VDDX I 79 XCLK O FSC O 80 N.C. 66 FSC O 75 CLK16M O 76 CLK12M O 77 CLK8M O 78 CLKX O ...
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Pin Definitions and Function (cont’d) Pin No. Symbol Input (I) Output (O) 60 SYNC I 72 RCLK O 57 RDO O Semiconductor Group Function Clock Synchronization If a clock is detected at the SYNC pin the FALC54 synchronizes to this ...
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Pin Definitions and Function (cont’d) Pin No. Symbol Input (I) Output (O) 71 RFSP/ O FREEZS 70 DLR O 68 XMFB O Semiconductor Group Function Receive Frame Synchronous Pulse/ Freeze Signaling If XC0.SFRZ is set to ‘0’ the Receive Frame ...
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Pin Definitions and Function (cont’d) Pin No. Symbol Input (I) Output (O) 59 XSIGM O 65 SYPR I 64 SYPX I 63 SCLKR I 62 SCLKX I Semiconductor Group Function Transmit Signaling Marker – Marks the transmit time-slots which are ...
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Pin Definitions and Function (cont’d) Pin No. Symbol Input (I) Output (O) 55 XDI I 69 DLX O 58 RSIGM O Semiconductor Group Function Transmit Data In Transmit data received from the system internal highway with 4096 kbit/s or 2048 ...
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Pin Definitions and Function (cont’d) Pin No. Symbol Input (I) Output (O) 67 RMFB O 61 XMFS I V 27, 37 26, 36 TDI I 21 TDO O 19 TMS I 20 ...
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Logic Symbol Figure 34 FALC54 Logic Symbol Semiconductor Group General Features T1 162 PEB 2254 11.96 ...
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Functional Block Diagram Figure 35 Functional Block Diagram PEB 2254 Semiconductor Group General Features T1 163 PEB 2254 11.96 ...
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System Integration The figures below show a multiple link application and a NT application. Figure 36 Multiple Link Application Semiconductor Group General Features T1 164 PEB 2254 11.96 ...
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Figure Application 4.6 Microprocessor Interface The communication between the CPU and the FALC54 is done via a set of directly accessible registers. The interface may be configured as Siemens/Intel or Motorola type with a selectable data bus ...
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Mixed Byte/Word Access to the FIFOs Reading from or writing to the internal FIFOs (RFIFO and XFIFO of each channel) can be done using a 8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode. Randomly mixed ...
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The assignment of registers with even/odd addresses to the data lines in case of 16-bit register access depends on the selected microprocessor interface mode: Siemens/Intel (Adr Motorola (Adr. n) Data Lines D15 n: even address Complete information ...
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Figure 38 FIFO Word Access (Intel Mode) Semiconductor Group General Features T1 168 PEB 2254 11.96 ...
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Figure 39 FIFO Word Access (Motorola Mode) Semiconductor Group General Features T1 169 PEB 2254 11.96 ...
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Interrupt Interface Special events in the FALC54 are indicated by means of a single interrupt output with programmable characteristics (open drain, push-pull; IPC register), which requests the CPU to read status information from the FALC transfer data from/to ...
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Masked Interrupts Visible in Status Registers The Global Interrupt Status register (GIS) indicates those interrupt status registers with active interrupt indications (GIS.ISR0-3). An additional mode can be selected via bit IPC.VIS. In this mode, masked interrupt status bits neither generate ...
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General Functions and Device Architecture T1 5.1 Functional Description T1 5.1.1 Receive Path Figure 41 Receive Clock System Receive Line Interface For data input, four different data types are supported: • Ternary coded signals received at multifunction ports RL1 ...
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Receive Equalizer The ITU-T I.431 recommendation requires a minimum loop length for T1 applications. The FALC54 meets this requirement by the integrated receive equalizer. Enabling and disabling the receive equalizer can be performed via a control bit. ...
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Table 14 Recommended Receiver Configuration Values Parameter Jitter free system clocks (16 MHz / 8 MHz / 4 MHz / 2 ...
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Jitter Attenuator Together with a PLL and a tunable crystal attenuation of received input jitter is done in the clock- and data-recovery and either in the received elastic buffer (2 frames the jitter attenuator “JATT“ block of figure ...
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Jitter Tolerance The FALC54 receiver’s tolerance to input jitter complies to ITU and Bellcore requirements and T1 application. Figure 44 shows the curves of different input jitter specifications stated above as well as the FALC54 performance. Figure 44 Jitter Tolerance ...
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Clock Generation and Clock Modes The high performance integrated Clock Generator meets the recommendations of ITU-T G.735 and I.431 in case of input jitter tolerance, jitter transfer characteristic and output jitter. The following table shows the clock modes with the ...
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Figure 45 Transmit Clock System Framer/Synchronizer The following functions are performed: • Synchronization on pulse frame • Synchronization on multiframe • Error indication when synchronization is lost. In this case, AIS is automatically sent to the system side and Remote ...
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If programmed and applicable to the selected multiframe format, CRC checking of the incoming data stream is done by generating check bits for a CRC multiframe according to the CRC 6 procedure (refer to ITU-T Rec. G.704). These bits are ...
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Figure 46 The Receive Elastic Store as Circularly Organized Memory Receive Signaling and Maintenance Controller The receive signaling controller can be programmed to operate in various signaling modes. The FALC54 will perform the following signaling and data link methods: • ...
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FALC54 can perform byte address recognition. All frames with valid addresses are forwarded directly via the Receive FIFO (RFIFO) to the system memory. The HDLC control-field, data in the I-field ...
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Transmit Path The inverse functions are performed for the transmit direction. The PCM data is received from the system internal highway at port XDI with 2048 kbit/s or 4096 kbit/s. The channel assignment is equivalent to the receive direction. ...
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Transmit Elastic Store The transmit elastic store with a size of 24 store for the PCM data to adapt the system clock (SCLKX) to the internally generated clock for the transmit data, and to re-translate channel structure used in the ...
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Transmit Line Interface The analog transmitter transforms the unipolar bit stream to ternary (alternate bipolar) return to zero signals of the appropriate programmable shape. The unipolar data is provided by pin XDI and the digital transmitter. Similar to the receive ...
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The FALC54 includes a programmable pulse shaper to satisfy the requirements of the AT&T Technical Advisory # 34 at the cross connect point for T1 applications. The amplitude of pulse shaper is individually programmable via the microprocessor interface to allow ...
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Transmit Line Monitor The transmit line monitor compares the transmit line pulses on XL1 and XL2 with the transmit input signals received on pins XL1M and XL2M. The monitor detects faults on the primary side of the transformer and protects ...
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Additional Functions Clear Channel Capability For support of common T1 applications, clear channels can be specified via the 3-byte register bank CCB1 … CCB3. In this mode the contents of selected channels will not be overwritten by bit robbing ...
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ISR0.PDEN. Generation of the interrupt status can be programmed either with the detection or with any change of state of the pulse density alarm (IPC.SCI). System Clocks and System Pulses for Transmitter and Receiver The FALC54 offers a flexible feature ...
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Operating Modes T1 General Activated with bit FMR1.PMOD = 1. PCM line bit rate : Single frame length : Framing frequency : Organization : Selection of one of the four permissible framing formats is performed by bits FMR4.FM0 and ...
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CCS = Common Channel Signaling CAS-CC = Channel Associated Signaling (Common Channel) CAS-BR = Channel Associated Signaling (Bit Robbing) For CCS, CAS-CC, and CAS-BR, different types of support are provided. Note: The internal HDLC- or CAS Controller supports all signaling ...
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Addition for F12 and F72 Format FT and FS bit conditions, i.e. pulse frame alignment and multiframe alignment can be handled separately if programmed via bit FMR2.SSP. Thus, a multiframe re-synchronization can be automatically initiated after detecting 2 errors out ...
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Figure 49 Influences on Synchronization Status Semiconductor Group General Functions and Device Architecture T1 192 PEB 2254 11.96 ...
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Figure 49 gives an overview of influences on synchronization status for the case of different external actions. Activation of auto-mode and non-auto mode is performed via bit FMR4.AUTO. Generally, for initiating resynchronization it is recommended to use bit: FMR0.EXLS first. ...
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Signaling The selection of the signaling scheme is done via bit FMR1.SIGM. • CCS FMR1.SIGM = 0 For Common Channel Signaling, the use of time-slot 24 is recommended. The use of CCS is permitted for all multiframe formats. • CAS-CC ...
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Multiframe Normally, this kind of multiframe structure only makes sense when using the CAS Robbed Bit Signaling. In addition, CCS and CAS-CC are also allowed. The multiframe alignment signal is located at the FS-bit position of every other ...
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Table 19 12-Frame Multiframe Structure Frame Number – – – – – – Semiconductor Group General Functions and Device Architecture ...
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Extended Superframe The use of the first bit of each frame for the multiframe alignment word, the data link bits, and the CRC bits is shown in table 20. Table 20 Extended Superframe Structure Multiframe Frame Number Multiframe Bit ...
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CRC6 Alarm Interrupt As an extension of the CRC6 checking algorithm the occurrence of a received CRC6 error may set an interrupt status. The CRC6 checking algorithm is enabled via bit FMR1.CRC. If not enabled, all check bits in the ...
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Multiframe The 72-multiframe is an alternate use of the FS-bit pattern and is used for carrying data link information. This is done by stealing some of redundant multiframing bits after the transmission of the 12-bit framing header (refer ...
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Table 21 72-Frame Multiframe Structure Frame Number – – – – – – – ...