IS61LV3216-12T Integrated Silicon Solution, IS61LV3216-12T Datasheet
IS61LV3216-12T
Available stocks
Related parts for IS61LV3216-12T
IS61LV3216-12T Summary of contents
Page 1
... Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory.A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61LV3216 is packaged in the JEDEC standard 44-pin 400-mil SOJ and 44-pin TSOP (Type 2). DECODER MEMORY ARRAY ...
Page 2
... IS61LV3216 PIN CONFIGURATIONS 44-Pin SOJ A14 A13 A12 A11 I/ I/O15 I/ I/O14 I/ I/O13 I/ I/O12 Vcc 11 34 GND GND 12 33 Vcc I/ I/O11 I/ I/O10 I/ I/ A10 ...
Page 3
... IS61LV3216 ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Supply Voltage with Respect to GND CC V Terminal Voltage with Respect to GND TERM T Storage Temperature STG P Power Dissipation Output Current (LOW) OUT OPERATING RANGE Range Ambient Temperature Commercial 0°C to +70°C DC ELECTRICAL CHARACTERISTICS Symbol Parameter ...
Page 4
... IS61LV3216 CAPACITANCE (1) Symbol Parameter C Input Capacitance IN C Input/Output Capacitance OUT Note: 1. Tested initially and after any design or process changes that may affect these parameters. READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Read Cycle Time RC t Address Access Time AA t Output Hold Time ...
Page 5
... IS61LV3216 AC WAVEFORMS (Address Controlled) ( READ CYCLE NO. 1 (1,2) ADDRESS D OUT PREVIOUS DATA VALID (1,3) READ CYCLE NO. 2 ADDRESS LZCE LB LZB HIGH-Z D OUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB Address is valid prior to or coincident with CE LOW transition. ...
Page 6
... IS61LV3216 WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Write Cycle Time Write End t SCE t Address Setup Time AW to Write End t Address Hold from Write End HA t Address Setup Time SA LB, UB Valid to End of Write t PWB WE Pulse Width t PWE t Data Setup to Write End ...
Page 7
... IS61LV3216 AC WAVEFORMS WRITE CYCLE NO. 1 (WE Controlled) ADDRESS CE LB (1) WRITE D IN HIGH-Z D OUT Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state WRITE = (CE) (LB) = (UB) (WE). Integrated Silicon Solution, Inc. — ...
Page 8
... Integrated Silicon Solution, Inc. is adequately protected under the circumstances. Copyright 1997 Integrated Silicon Solution, Inc. Reproduction in whole or in part, without the prior written consent of Integrated Silicon Solution, Inc., is prohibited. 8 ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed (ns) Order Part No. 12 IS61LV3216-12TI 12 IS61LV3216-12KI 15 IS61LV3216-15TI 15 IS61LV3216-15KI 20 ...