IS42S16400-7T Integrated Silicon Solution, IS42S16400-7T Datasheet

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IS42S16400-7T

Manufacturer Part Number
IS42S16400-7T
Description
1M bits x 16 bits x 4 banks(64-MBIT)synchronous graphics RAM
Manufacturer
Integrated Silicon Solution
Datasheet

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IS42S16400
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
FEATURES
• Clock frequency: 166, 133, 100 MHz
• Fully synchronous; all signals referenced to a
• Internal bank for hiding row access/precharge
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
• Programmable burst sequence:
• Self refresh modes
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
• Burst termination by burst stop and precharge
• Byte controlled by LDQM and UDQM
• Industrial temperature availability
• Package: 400-mil 54-pin TSOP II
PIN DESCRIPTIONS
This document contains TARGET SPECIFICATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best
possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
TARGET SPECIFICATION Rev. C
05/04/01
A0-A11
BA0, BA1
I/O0 to I/O15
CLK
CKE
CS
RAS
CAS
positive clock edge
– (1, 2, 4, 8, full page)
Sequential/Interleave
operations capability
command
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
Address Input
Bank Select Address
OVERVIEW
ISSI
as 1,048,576 bits x 16-bit x 4-bank for improved
performance. The synchronous DRAMs achieve high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
PIN CONFIGURATIONS
54-Pin TSOP (Type II)
WE
LDQM
UDQM
Vcc
GND
Vcc
GND
NC
's 64Mb Synchronous DRAM IS42S16400 is organized
Q
Q
GNDQ
GNDQ
VCCQ
VCCQ
LDQM
VCC
VCC
VCC
CAS
RAS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
BA0
BA1
A10
WE
CS
A0
A1
A2
A3
Write Enable
Lower Bye, Input/Output Mask
Upper Bye, Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
FINAL PRODUCTION
ISSI
MAY 2001
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
GND
I/O15
GNDQ
I/O14
I/O13
VCCQ
I/O12
I/O11
GNDQ
I/O10
I/O9
VCCQ
I/O8
GND
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
GND
®
1

Related parts for IS42S16400-7T

IS42S16400-7T Summary of contents

Page 1

... ISSI FINAL PRODUCTION MAY 2001 OVERVIEW ISSI 's 64Mb Synchronous DRAM IS42S16400 is organized as 1,048,576 bits x 16-bit x 4-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. ...

Page 2

... IS42S16400 GENERAL DESCRIPTION The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 4,096 rows by 256 columns by 16 bits. The 64Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode ...

Page 3

... IS42S16400 PIN FUNCTIONS Symbol Pin No. Type A0-A11 Input Pin 22, 35 BA0, BA1 20, 21 Input Pin CAS 17 Input Pin CKE 37 Input Pin CLK 38 Input Pin CS 19 Input Pin I/ 10, I/O Pin I/O15 11,13, 42, 44, 45, 47, 48, 50, 51, 53 LDQM, 15, 39 Input Pin ...

Page 4

... IS42S16400 FUNCTION (In Detail) A0-A11 are address inputs sampled during the ACTIVE (row-address A0-A11) and READ/WRITE command (A0-A7 with A10 defining auto PRECHARGE). A10 is sampled during a PRECHARGE command to determine if all banks are to be PRECHARGED (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command ...

Page 5

... IS42S16400 enabled or disabled. AUTO PRECHARGE does not apply except in full-page burst mode. Upon completion of the READ or WRITE burst, a precharge of the bank/row that is addressed is automatically performed. AUTO REFRESH COMMAND This command executes the AUTO REFRESH operation. The row address and bank to be refreshed are automatically generated during this operation ...

Page 6

... IS42S16400 TRUTH TABLE – COMMANDS AND DQM OPERATION FUNCTION COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank/column, start READ burst) WRITE (Select bank/column, start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH ...

Page 7

... IS42S16400 TRUTH TABLE – CKE (1-4) CURRENT STATE COMMANDn Power-Down X Self Refresh X Clock Suspend X (5) Power-Down COMMAND INHIBIT or NOP (6) Self Refresh COMMAND INHIBIT or NOP (7) Clock Suspend X All Banks Idle COMMAND INHIBIT or NOP All Banks Idle AUTO REFRESH Reading or Writing VALID See TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n NOTES: 1. CKEn is the logic state of CKE at clock edge n ...

Page 8

... IS42S16400 NOTE: 1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table - CKE) and after t previous state was SELF REFRESH). 2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state ...

Page 9

... IS42S16400 TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK m CURRENT STATE COMMAND (ACTION) Any COMMAND INHIBIT (NOP/Continue previous operation) NO OPERATION (NOP/Continue previous operation) Idle Any Command Otherwise Allowed to Bank m Row ACTIVE (Select and activate row) Activating, READ (Select column and start READ burst) ...

Page 10

... IS42S16400 7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been inter- rupted by bank m’s burst. ...

Page 11

... IS42S16400 ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Maximum Supply Voltage CC MAX V Maximum Supply Voltage for Output Buffer CCQ MAX V Input Voltage IN V Output Voltage OUT P Allowable Power Dissipation D MAX I Output Shorted Current CS T Operating Temperature OPR T Storage Temperature STG DC RECOMMENDED OPERATING CONDITIONS ...

Page 12

... IS42S16400 DC ELECTRICAL CHARACTERISTICS Symbol Parameter I Input Leakage Current IL I Output Leakage Current OL V Output High Voltage Level OH V Output Low Voltage Level OL I Operating Current (1,2) CC1 I Precharge Standby Current CC2P I (In Power-Down Mode) CC2PS I Precharge Standby Current CC2N I (In Non Power-Down Mode) ...

Page 13

... IS42S16400 AC ELECTRICAL CHARACTERISTICS Symbol Parameter t Clock Cycle Time CK3 t CK2 (4) t Access Time From CLK AC3 t AC2 t CLK HIGH Level Width CHI t CLK LOW Level Width CL t Output Data Hold Time OH3 t OH2 t Output LOW Impedance Time LZ (5) t Output HIGH Impedance Time ...

Page 14

... IS42S16400 OPERATING FREQUENCY / LATENCY RELATIONSHIPS SYMBOL PARAMETER — Clock Cycle Time — Operating Frequency t READ/WRITE command to READ/WRITE command CCD t CKE to clock disable or power-down entry mode CKED t CKE to clock enable or power-down exit setup mode PED t DQM to input data delay DQD t DQM to data mask during WRITEs ...

Page 15

... IS42S16400 FUNCTIONAL DESCRIPTION The 64Mb SDRAMs (1 Meg banks) are quad-bank DRAMs which operate at 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. ...

Page 16

... IS42S16400 REGISTER DEFINITION Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS\ latency, an operating mode and a write burst mode, as shown in MODE REGISTER DEFINITION. The mode register is programmed via the LOAD MODE ...

Page 17

... IS42S16400 Burst Length Read and write accesses to the SDRAM are burst ori- ented, with the burst length being programmable, as shown in MODE REGISTER DEFINITION. The burst length determines the maximum number of column loca- tions that can be accessed for a given READ or WRITE command. Burst lengths locations are ...

Page 18

... IS42S16400 CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge ...

Page 19

... IS42S16400 OPERATION BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Activating Specific Row Within Specific Bank). ...

Page 20

... IS42S16400 READS READ bursts are initiated with a READ command, as shown in the READ COMMAND diagram. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst ...

Page 21

... IS42S16400 same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in the READ to PRECHARGE diagram for each possible CAS latency; data element either the last of a burst of four or the last desired of a longer burst ...

Page 22

... IS42S16400 Consecutive READ Bursts T0 CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - NOP NOP NOP READ n+1 OUT OUT NOP NOP READ BANK, COL ...

Page 23

... IS42S16400 Random READ Accesses T0 CLK COMMAND READ BANK, ADDRESS COL CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — 1-800-379-4774 TARGET SPECIFICATION Rev. C 05/04/ READ READ READ BANK, BANK, BANK, COL b COL m COL ...

Page 24

... IS42S16400 RW1 - READ to WRITE CLK DQM COMMAND ADDRESS DQ RW2 - READ to WRITE With Extra Clock Cycle T0 CLK DQM COMMAND READ BANK, ADDRESS COL READ NOP NOP BANK, COL NOP NOP NOP OUT Integrated Silicon Solution, Inc. — 1-800-379-4774 ...

Page 25

... IS42S16400 READ to PRECHARGE T0 T1 CLK COMMAND READ NOP BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — 1-800-379-4774 TARGET SPECIFICATION Rev. C 05/04/ NOP NOP PRECHARGE cycle ...

Page 26

... IS42S16400 READ Burst Termination T0 CLK COMMAND READ BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - BURST NOP NOP NOP TERMINATE n+1 OUT OUT BURST NOP NOP TERMINATE ...

Page 27

... IS42S16400 WRITEs WRITE bursts are initiated with a WRITE command, as shown in WRITE Command diagram. WRITE Command CLK HIGH - Z CKE CS RAS CAS WE A0-A7 COLUMN ADDRESS A8, A9, A11 AUTO PRECHARGE A10 NO PRECHARGE BA0, BA1 BANK ADDRESS The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access ...

Page 28

... IS42S16400 WRITE Burst COMMAND ADDRESS WRITE to WRITE Random WRITE Cycles COMMAND ADDRESS CLK WRITE NOP NOP BANK, COL n CLK COMMAND WRITE NOP BANK, ADDRESS COL n DON'T CARE CLK WRITE WRITE WRITE ...

Page 29

... IS42S16400 WRITE to READ T0 CLK COMMAND WRITE BANK, ADDRESS COL WRITE to PRECHARGE ( CLK DQM COMMAND WRITE BANK a, ADDRESS COL Integrated Silicon Solution, Inc. — 1-800-379-4774 TARGET SPECIFICATION Rev. C 05/04/ NOP READ NOP BANK, COL n+1 IN ...

Page 30

... IS42S16400 WRITE to PRECHARGE ( CLK DQM COMMAND WRITE BANK a, ADDRESS COL WRITE Burst Termination COMMAND ADDRESS 15ns NOP NOP PRECHARGE BANK (a or all n CLK BURST WRITE TERMINATE BANK, COL DON'T CARE Integrated Silicon Solution, Inc. — ...

Page 31

... IS42S16400 PRECHARGE The PRECHARGE command (see figure) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (t the PRECHARGE command is issued. Input A10 deter- mines whether one or all banks are to be precharged, and in the case where only one bank precharged, inputs BA0, BA1 select the bank ...

Page 32

... IS42S16400 CLOCK SUSPEND Clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. ...

Page 33

... IS42S16400 BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation ( ...

Page 34

... IS42S16400 WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after t where t begins when the READ to bank m is registered. ...

Page 35

... IS42S16400 INITIALIZE AND LOAD MODE REGISTER CLK CKS CKH CKE CMH CMS CMH CMS COMMAND NOP PRECHARGE DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 ALL BANKS Power-up: V Precharge CC and CLK stable all banks T = 100µ ...

Page 36

... IS42S16400 POWER-DOWN MODE CYCLE T0 CLK t t CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Precharge all All banks idle, enter active banks power-down mode CAS latency = 2, 3 ...

Page 37

... IS42S16400 CLOCK SUSPEND MODE CLK CKS CKH CKE t t CMS CMH COMMAND READ NOP t t CMS CMH DQM/ DQML, DQMH (2) A0-A9, A11 COLUMN A10 BA0, BA1 BANK DQ CAS latency = 2, burst length = 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 TARGET SPECIFICATION Rev ...

Page 38

... IS42S16400 AUTO-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK ( High-Z CAS latency = Auto NOP NOP Refresh RFC Integrated Silicon Solution, Inc. — ...

Page 39

... IS42S16400 SELF-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE NOP DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Precharge all active banks refresh mode CAS latency = 2, 3 Integrated Silicon Solution, Inc. — 1-800-379-4774 TARGET SPECIFICATION Rev ...

Page 40

... IS42S16400 READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS ...

Page 41

... IS42S16400 READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Integrated Silicon Solution, Inc. — 1-800-379-4774 TARGET SPECIFICATION Rev ...

Page 42

... IS42S16400 SINGLE READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC ...

Page 43

... IS42S16400 SINGLE READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Integrated Silicon Solution, Inc. — 1-800-379-4774 TARGET SPECIFICATION Rev ...

Page 44

... IS42S16400 ALTERNATING BANK READ ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK BANK 0 RCD t RRD t - BANK 0 ...

Page 45

... IS42S16400 READ - FULL-PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/ DQML, DQMH A0-A9, A11 ROW COLUMN A10 ROW BA0, BA1 BANK DQ t RCD Integrated Silicon Solution, Inc. — 1-800-379-4774 TARGET SPECIFICATION Rev ...

Page 46

... IS42S16400 READ - DQM OPERATION CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD READ NOP NOP ...

Page 47

... IS42S16400 WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Integrated Silicon Solution, Inc. — 1-800-379-4774 TARGET SPECIFICATION Rev ...

Page 48

... IS42S16400 WRITE - WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC ...

Page 49

... IS42S16400 SINGLE WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Integrated Silicon Solution, Inc. — ...

Page 50

... IS42S16400 SINGLE WRITE - WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND (3) ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS ...

Page 51

... IS42S16400 ALTERNATING BANK WRITE ACCESS CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK BANK 0 RCD t RRD ...

Page 52

... IS42S16400 WRITE - FULL PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD WRITE NOP ...

Page 53

... IS42S16400 WRITE - DQM OPERATIOON CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD Integrated Silicon Solution, Inc. — 1-800-379-4774 TARGET SPECIFICATION Rev. C ...

Page 54

... MHz 100 MHz 54 Speed (ns) Order Part No. 6 IS42S16400-6T 7 IS42S16400-7T 10 IS42S16400-10T Speed (ns) Order Part No. 7 IS42S16400-7TI 10 IS42S16400-10TI Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI Package 400-mil TSOP II 400-mil TSOP II 400-mil TSOP II Package 400-mil TSOP II 400-mil TSOP II ISSI ...

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