AK4586VQ Asahi Kasei Microsystems, AK4586VQ Datasheet

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AK4586VQ

Manufacturer Part Number
AK4586VQ
Description
Manufacturer
Asahi Kasei Microsystems
Datasheet

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ASAHI KASEI
The AK4586 is a single chip CODEC that includes two channels of ADC and six channels of DAC. The
ADC outputs 24bit data and the DAC accepts up to 24bit input data. The ADC has the Enhanced Dual Bit
architecture with wide dynamic range. The DAC introduces the new developed Advanced Multi-Bit
architecture, and achieves wider dynamic range and lower outband noise.
The AK4586 also has a digital audio receiver (DIR) compatible with 96kHz, 24bits. The AK4586 can
automatically detect a Non-PCM bit stream. The digital audio output can be selected from the ADC output
or the digital input. Control may be set directly by programmed through a separate serial interface.
The AK4586 has a dynamic range of 100dB for ADC, 106dB for DAC and is well suited for digital surround
for home theater and car audio. The AK4586 also has the balance volume control corresponding to the
AC-3 system. The AK4586 is available in a small 44pin LQFP package which will reduce system space.
MS0097-E-01
*AC-3 is a trademark of Dolby Laboratories.
2ch 24bit ADC
6ch 24bit DAC
4 inputs 24bit DIR
- 64x Oversampling
- Sampling Rate up to 96kHz
- Linear Phase Digital Anti-Alias Filter
- Single-Ended Input
- S/(N+D): 90dB
- Dynamic Range, S/N: 100dB
- Digital HPF for offset cancellation
- Overflow flag
- 128x Oversampling
- Sampling Rate up to 96kHz
- 24bit 8 times Digital Filter
- Single-Ended Outputs
- On-chip Switched-Capacitor Filter
- S/(N+D): 90dB
- Dynamic Range, S/N: 106dB
- Individual channel digital volume with 256 levels and 0.5dB step
- Soft mute
- Zero Detect Function
- Supports IEC60958 consumer mode, S/PDIF,
- Low jitter Analog PLL
- PLL Lock Range: 32k
- Clock Source: PLL or X'tal
- 4 channel Receivers input and 1 through transmission output
- De-emphasis for 32kHz, 44.1kHz and 48kHz
- Dedicated Detect Pins
- Supports up to 24bit Audio Data Format
- Audio I/F: Master or Slave Mode
- 32bits Channel Status Buffer
EIAJ CP1201 consumer mode
Non-PCM Bit Stream Detect, DTS-CD Bit Stream Detect,
Validity Flag Detect, 96kHz Sampling Detect,
Unlock & Parity Error Detect, Emphasis Detect, fs change Detect
GENERAL DESCRIPTION
Multi-channel Audio CODEC with DIR
FEATURES
- 1 -
96kHz
AK4586
[AK4586]
2001/12

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AK4586VQ Summary of contents

Page 1

ASAHI KASEI The AK4586 is a single chip CODEC that includes two channels of ADC and six channels of DAC. The ADC outputs 24bit data and the DAC accepts up to 24bit input data. The ADC has the Enhanced Dual ...

Page 2

ASAHI KASEI - Burst Preamble bit Pc, Pd Buffer for Non-PCM bit stream - Master Clock Outputs:128fs/256fs/512fs I/F format: MSB justified, LSB justified(20bit,24bit), I High Jitter Tolerance TTL Level Digital I/F 4-wire Serial and I Extenal Master Clock Input: - ...

Page 3

... Ordering Guide AK4586VQ AKD4586 Pin Layout XTO XTI/EXTCLK DVDD DVSS TVDD TX MCKO LRCK BICK SDTO SDTI1 MS0097-E-01 -40 +85 C 44pin LQFP(0.8mm pitch) Evaluation Board for AK4586 AK4586VQ 6 7 Top View [AK4586] 33 RIN 32 LIN 31 ROUT1 30 LOUT1 29 ROUT2 28 LOUT2 27 ROUT3 ...

Page 4

ASAHI KASEI Compatibility with AK4527B/29 Functions ADC S/(N+D) ADC Dynamic Range, S/N DAC channel Master mode Parallel mode Read operation for internal register Chip address at 4-wire serial mode Compatibility with AK4112A Functions Power supply Rock range Master clock output ...

Page 5

ASAHI KASEI No. Pin Name I/O 1 XTO O X'tal Output Pin 2 XTI I X'tal Input Pin EXTCLK I External Master Clock Input Pin 3 DVDD - Digital Power Supply Pin, 4.5V 5.5V 4 DVSS - Digital Ground Pin, ...

Page 6

ASAHI KASEI No. Pin Name I/O 23 VREFH I Positive Voltage Reference Input Pin, AVDD 24 VCOM O Common Voltage Output Pin, AVDD/2 Large external capacitor around 2.2µF is used to reduce power-supply noise. 25 DZF1 O Zero Input Detect ...

Page 7

ASAHI KASEI (AVSS, DVSS, PVSS=0V; Note 4) Parameter Power Supplies Analog Digital PLL Output buffer |AVSS-DVSS| |AVSS-PVSS| Input Current (any pins except for supplies) Analog Input Voltage Digital Input Voltage (XTI/EXTCLK, SDTI1-3, CDTI/SDA, CCLK/SCL, CSN/CAD0 pins) (LRCK, BICK, CDTO/CAD1 pins) ...

Page 8

ASAHI KASEI (Ta=25 C; AVDD, DVDD, PVDD, TVDD=5V; AVSS, DVSS=0V; VREFH=AVDD; fs=48kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz 20kHz at fs=48kHz, 20Hz~40kHz at fs=96kHz; unless otherwise specified) Parameter ADC Analog Input Characteristics Resolution S/(N+D) (-0.5dBFS) fs=48kHz fs=96kHz DR (-60dBFS) ...

Page 9

ASAHI KASEI (Ta=25 C; AVDD, DVDD, PVDD=4.5 5.5V; TVDD=2.7 5.5V; fs=48kHz) Parameter ADC Digital Filter (Decimation LPF): Passband (Note 14) Stopband Passband Ripple Stopband Attenuation Group Delay (Note 15) Group Delay Distortion ADC Digital Filter (HPF): Frequency Response (Note 14) ...

Page 10

ASAHI KASEI (Ta=25 C; AVDD, DVDD, PVDD=4.5 5.5V; TVDD=2.7 5.5V; C Parameter Master Clock Timing Crystal Resonator Frequency External Clock 256fsn, 128fsd: Pulse Width Low Pulse Width High 384fsn, 192fsd: Pulse Width Low Pulse Width High 512fsn, 256fsd: Pulse Width ...

Page 11

ASAHI KASEI Parameter Audio Interface Timing (Slave mode) TDM= “0” BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “ ” BICK “ ” to LRCK Edge LRCK to SDTO(MSB) BICK “ ” to SDTO SDTI1-3, ...

Page 12

... The AK4586 can be reset by bringing PDN “L” to “H” upon power-up. 24. These cycles are the number of LRCK rising from PDN rising registered trademark of Philips Semiconductors. Purchase of Asahi Kasei Microsystems Co., Ltd patent to use the components in the I specifications defined by Philips. ...

Page 13

ASAHI KASEI Timing Diagram MCLK MCKO tMCKH LRCK BICK MCLK LRCK BICK MS0097-E-01 1/fCLK tCLKH tCLKL 1/fMCKO tMCKL dMCK = tMCKH x fMCK x 100 1/fs tLRH tLRL Duty = tLRH 100 tBCK tBCKH tBCKL Clock Timing ...

Page 14

ASAHI KASEI LRCK tBLR BICK tLRS SDTO SDTI Audio Interface Timing (Slave mode, TDM= “0”) LRCK tBLR BICK SDTO SDTI Audio Interface Timing (Slave mode, TDM= “1”) LRCK tMBLR BICK SDTO SDTI MS0097-E-01 tLRB tSDS tSDH tLRB tSDS tSDH tSDS ...

Page 15

ASAHI KASEI CSN CCLK CDTI CDTO WRITE/READ Command Input Timing (4-wire serial mode) CSN CCLK CDTI D3 CDTO WRITE Data Input Timing (4-wire serial mode) CSN CCLK CDTI A1 Hi-Z CDTO READ Data Output Timing 1 (4-wire serial mode) MS0097-E-01 ...

Page 16

ASAHI KASEI CSN CCLK CDTI CDTO D3 READ Data Output Timing 2 (4-wire serial mode) SDA tLOW tR tBUF SCL tHD:STA tHD:DAT Stop Start tPD PDN SDTO MS0097-E-01 tCSW tCSH tHIGH tF tSU:DAT tSU:STA Start 2 I ...

Page 17

ASAHI KASEI Non-PCM (AC-3, MPEG, etc.), DTS-CD Bitstream Detect The AK4586 has the Non-PCM steam auto detect function. When the 32bit mode Non-PCM preamble based on Dolby “AC-3 Data Stream in IEC60958 Interface” is detected, the AUTO bit goes to ...

Page 18

ASAHI KASEI Clock mode AFS96 X’tal mode x 0 PLL mode 1 Table 3. Sampling Speed Mode (x: Don’t care) Mode ICKS1 Table 4. Master Clock Input Frequency Select (X’tal mode) (In the x’tal mode, ADC ...

Page 19

ASAHI KASEI Clock Source The following circuits are available to feed the clock to XTI pin of AK4586. 1) X’tal Note: External capacitance depends on the crystal oscillator (Typ. 10-40pF) 2) External clock External Clock(5V) External Clock(3.3V) Note: 3.3V external ...

Page 20

ASAHI KASEI Sampling Frequency and Pre-emphasis Detect The AK4586 outputs the encoded information of sampling frequency and pre-emphasis in channel status to FS0, FS1 and PEM bits in control register. These information are output from channel 1 at default. It ...

Page 21

ASAHI KASEI De-emphasis Filter Control The AK4586 includes the digital de-emphasis filter (tc=50/15µs) by IIR filter corresponding to three sampling frequencies (32kHz, 44.1kHz and 48kHz). When DEAU bit = “1”, the de-emphasis filter is enabled automatically by sampling frequency and ...

Page 22

ASAHI KASEI Biphase Input and Through Output Four receiver inputs (RX1-4) are available. Each input includes amplifier corresponding to unbalance mode and can accept the signal of 200mV or more. IPS1-0 selects the receiver channel (Table 11), and OPS1-0 selects ...

Page 23

ASAHI KASEI Biphase signal input/output circuit 75 Coax Figure 6. Consumer Input Circuit (Coaxial Input) Note 1: In case of coaxial input coupling level to this input from the next RX input line pattern exceeds 50mV, there is ...

Page 24

ASAHI KASEI Error Handling There are the following eight factors which INT1-0 pins go to “H”. 1. UNLOCK: “1” when the PLL goes UNLOCK state. The AK4586 loses lock when the distance between two preambles is not correct or when ...

Page 25

ASAHI KASEI Error (UNLOCK, PAR,..) INT0 pin INT1 pin Register (PAR,STC) Register (except PAR,STC) Command MCKO,BICK,LRCK (UNLOCK) MCKO,BICK,LRCK (except UNLOCK) SDTO (UNLOCK) SDTO (PAR error) SDTO (others) MS0097-E-01 (Error) Hold Time (max: 4096/fs) Hold Time = 0 Hold ”1” READ ...

Page 26

ASAHI KASEI Release Muting Figure 10. Error Handling Sequence Example MS0097-E-01 PDN pin ="L" to "H" Initialize Read 0EH INT0/1 pin ="H" No Yes Mute DAC output Read 0EH (Each Error Handling) No INT0/1 pin ="H" Yes - 26 - ...

Page 27

ASAHI KASEI Audio Serial Interface Format Eight serial data formats can be selected by the DIF2-0 bits as shown in Table 14 at the SLAVE pin “L”. If the SLAVE pin is “H”, the AK4586 is fixed in the slave ...

Page 28

ASAHI KASEI The audio serial interface format becomes the TDM I/F format if TDM bit is set to “1”. In the TDM mode, the serial data of all DAC (six channels) is input to the SDTI1 pin. The input data ...

Page 29

ASAHI KASEI LRCK BICK (64fs SDTO(0) 23:MSB, 0:LSB SDTI(I) 23:MSB, 0:LSB LRCK BICK (64fs SDTO(0) 23:MSB, 0:LSB ...

Page 30

ASAHI KASEI LRCK BICK(256fs) SDTO( Lch 32 BICK SDTI1( BICK LRCK BICK(256fs) SDTO( Lch 32 BICK SDTI1( BICK MS0097-E-01 256 BICK ...

Page 31

ASAHI KASEI LRCK(mode 12) LRCK(mode 14) BICK(256fs) SDTO( Lch 32 BICK SDTI1( BICK LRCK(mode 13) LRCK(mode 15) BICK(256fs) SDTO( Lch 32 BICK SDTI1( BICK MS0097-E-01 256 ...

Page 32

ASAHI KASEI Digital High Pass Filter The ADC has a digital high pass filter for DC offset cancel. The cut-off frequency of the HPF is 1.0Hz at fs=48kHz and also scales with sampling rate (fs). Overflow Detection The AK4586 has ...

Page 33

ASAHI KASEI Digital Attenuator The AK4586 has channel-independent digital attenuator (256 levels, 0.5dB step). Attenuation level of each channel can be set by each ATT7-0 bits (Table 17). ATT7-0 Table 17. Attenuation level of digital attenuator Transition time between set ...

Page 34

ASAHI KASEI Soft mute operation Soft mute operation is performed at digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by - during 1024 LRCK cycles. When the SMUTE bit is returned to “0”, the ...

Page 35

ASAHI KASEI Serial Control Interface (1) 4-wire Serial Control Mode (I2C = “L”) The internal registers may be either written or read by the 4-wire µP interface pins: CSN, CCLK, CDTI & CDTO. The data on this interface consists of ...

Page 36

ASAHI KASEI 2 (2) I C-bus Control Mode (I2C= “H”) 2 AK4586 supports the standard-mode C-bus system (max:400kHz). (2)-1. WRITE Operations Figure 22 shows the data transfer sequence at the I HIGH to LOW transition on the ...

Page 37

ASAHI KASEI (2)-2. READ Operations Set R/W bit = “1” for the READ operation of the AK4586. After transmission of a data, the master can read next address’s data by generating the acknowledge instead of terminating the write cycle after ...

Page 38

ASAHI KASEI SDA SCL S start condition DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER SCL FROM MASTER S START CONDITION SDA SCL MS0097-E-01 Figure 28. START and STOP conditions Figure 29. Acknowledge on the I C-bus ...

Page 39

ASAHI KASEI Mapping of Program Registers Addr Register Name 00H Power Down & Reset 01H Path Control 02H Clock Mode Control 03H Output Control 04H Receiver Control XFS96 05H I/F Format & ATT Speed 06H LOUT1 Volume Control 07H ROUT1 ...

Page 40

ASAHI KASEI Register Definitions Addr Register Name 00H Power Down & Reset R/W Default RSTN: Internal timing reset 0: Reset. DZF1-2 pins go to “H”, but registers are not initialized. 1: Normal operation PWDAN: Power-down control of DAC1-3 0: Power-down ...

Page 41

ASAHI KASEI Addr Register Name 02H Clock Mode Control R/W Default CM1-0: Master Clock Operation Mode Select (Table 1) Default: “00”, mode 0 OCKS1-0: Master Clock Output Frequency Select at PLL mode (Table 2) Default: “00”, mode 0 ICKS1-0: Master ...

Page 42

ASAHI KASEI Addr Register Name 03H Output Control R/W Default DZFM2-0: Zero detect mode select (Table 16) Initial: “111”, disable OVFE: Overflow detection enable 0: Disable, pin#20 becomes DZF2 pin. 1: Enable, pin#20 becomes OVF pin. BCU: Block Start and ...

Page 43

ASAHI KASEI Addr Register Name 04H Receiver Control R/W Default DEM1-0: De-emphasis Control (Table 9) The setting of DEM1-0 bits is ignored at DEAU bit “1”. Default: “01”, OFF DEAU: De-emphasis Auto Detect Enable 0: Disable 1: Enable EFH1-0: Interrupt ...

Page 44

ASAHI KASEI Addr Register Name 06H LOUT1 Volume Control 07H ROUT1 Volume Control 08H LOUT2 Volume Control 09H ROUT2 Volume Control 0AH LOUT3 Volume Control 0BH ROUT3 Volume Control R/W Default ATT7-0: Attenuation Level (Table 17) Default: all “0” (0dB) ...

Page 45

ASAHI KASEI Addr Register Name D7 0CH INT0 Mask MRFS0 R/W R/W Default 1 MULK0: Mask Enable for UNLOCK bit (Default Mask disable 1: Mask enable MPAR0: Mask Enable for PAR bit (Default Mask disable 1: ...

Page 46

ASAHI KASEI Addr Register Name D7 0EH Receiver status 1 RFS96 R/W RD Default 0 UNLOCK: PLL Lock Status 0: Lock PAR: Parity Error or Biphase Error Status 0: No error It is “1” if parity error or biphase error ...

Page 47

ASAHI KASEI Addr Register Name 10H Channel Status Byte 0 11H Channel Status Byte 1 12H Channel Status Byte 2 13H Channel Status Byte 3 R/W Default C31-0: Channel Status Byte 3-0 Addr Register Name 14H Burst Preamble Pc Byte ...

Page 48

ASAHI KASEI Burst Preambles in Non-PCM Bitstreams preamble Aux Preamble word Length of field Pa 16 bits Pb 16 bits Pc 16 bits Pd 16 bits MS0097-E-01 sub-frame of IEC60958 ...

Page 49

ASAHI KASEI Bits of Pc Value Contents 0-4 data type 0 NULL data 1 Dolby AC-3 data 2 reserved 3 PAUSE 4 MPEG-1 Layer1 data 5 MPEG-1 Layer2 or 3 data or MPEG-2 without extension 6 MPEG-2 data with extension ...

Page 50

ASAHI KASEI Non-PCM Bitstream timing 1) When Non-PCM preamble is not coming within 4096 frames, PDN pin Bit stream AUTO bit Pc Register “0” Pd Register “0” 2) When Non-PCM bitstream stops (when MULK0=0), INT0 ...

Page 51

ASAHI KASEI Figure 34 shows the system connection diagram. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. Condition: TVDD=3.3V, Master mode, 4-wire serial control mode, DZFM2-0 = “100” Power-down Control ...

Page 52

ASAHI KASEI 1. Grounding and Power Supply Decoupling The AK4586 requires careful attention to power supply and grounding arrangements. AVDD, DVDD and PVDD are usually supplied from analog supply in system. Alternatively if AVDD, DVDD and PVDD are supplied separately, ...

Page 53

ASAHI KASEI 44pin LQFP (Unit: mm) 12.80 0.30 10. 0.37 0.10 0.15 Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: MS0097-E-01 PACKAGE 1.70max ...

Page 54

... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0097-E-01 MARKING AK4586VQ XXXXXXX 1 1) Pin #1 indication 2) Date Code: XXXXXXX(7 digits) 3) Marking Code: AK4586VQ 4) Asahi Kasei Logo IMPORTANT NOTICE - 54 - [AK4586] 2001/12 ...

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