AK4563AVF Asahi Kasei Microsystems, AK4563AVF Datasheet

no-image

AK4563AVF

Manufacturer Part Number
AK4563AVF
Description
Manufacturer
Asahi Kasei Microsystems
Datasheet
ASAHI KASEI
MS0067-E-02
The AK4563A is low power operation, 16bit CODEC that include 4ch ADC and 2ch DAC. The AK4563A
also includes ALC (Automatic Level Control) circuit, therefore is suitable for microphone application and
etc. As the ALC circuit can be stopped by controlling µP, IPGA can also be used as the manual volume.
Digital I/F can be input/output from 1.5V to 3.0V by external power supply. The AK4563A can be
powered-down by each block, therefore the AK4563A is suitable to low power dissipation in system.
1. Resolution : 16bits
2. Recording Functions
3. Playback Function
4. Power Management
5. CODEC (ADC: 4ch, DAC: 2ch)
6. Master Clock: 256fs/384fs
7. Sampling Rate: 8kHz ∼ 50kHz
8. Audio Data Interface Format: MSB-First, 2’s compliment (AK4516A Compatible)
9. Power Supply
10. Power Supply Current
11. Ta = -20 ∼ 85 ºC
12. Package: 28pin VSOP
• 4ch Analog Input PGA (Programmable Gain Amplifier)
• Digital ALC (Automatic Level Control) circuit
• FADEIN / FADEOUT
• Digital HPF for DC-offset cancellation (fc=3.7Hz@fs=48kHz)
• Peak-Meter Output (2ch)
• Digital De-emphasis Filter (tc = 50/15µs, fs=32k, 44.1k and 48kHz)
• Single-ended Inputs/Outputs
• Input / Output Level: 1.5Vpp@VREF=2.5V (= 0.6 x VREF)
• S/(N+D): 83dB(ADC), 86dB(DAC) @VREF=2.5V
• DR, S/N: 87dB(ADC), 91dB(DAC) @VREF=2.5V
• ADC: 16bit MSB justified, 16bit LSB justified, I
• DAC: 16bit MSB justified, 16bit LSB justified, I
• CODEC, PGA: 2.3 ∼ 3.0V (typ.2.5V)
• Digital I/F: 1.5 ∼ 3.0V(typ.2.5V)
• ALL Power ON: 18mA
• (ALC + ADC) x 4ch: 13.5mA
• DAC: 5.5mA
Low Power 16bit 4ch ADC & 2ch DAC with ALC
GENERAL DESCRIPTION
FEATURES
- 1 -
2
2
S
S
AK4563A
[AK4563A]
2004/12

Related parts for AK4563AVF

AK4563AVF Summary of contents

Page 1

ASAHI KASEI Low Power 16bit 4ch ADC & 2ch DAC with ALC The AK4563A is low power operation, 16bit CODEC that include 4ch ADC and 2ch DAC. The AK4563A also includes ALC (Automatic Level Control) circuit, therefore is suitable for ...

Page 2

ASAHI KASEI INTL0 EXTL IPGA0 LIN INTR0 EXTR RIN INTL1 IPGA1 INTR1 LOUT ROUT VCOM VREF VA AGND MS0067-E-02 ADC0 HPF HPF ADC1 DAC De-emp Control Register I/F CSN CCLK CDTI CDTO Figure 1. AK4563A Block Diagram - 2 - ...

Page 3

... ASAHI KASEI Ordering Guide -20 ∼ +85°C AK4563AVF AKD4563A Evaluation board for AK4563A Pin Layout LOUT 1 ROUT 2 INTL1 3 INTR1 4 INTL0 5 6 INTR0 EXTL 7 EXTR 8 LIN 9 RIN 10 VCOM 11 AGND VREF 14 MS0067-E-02 28pin VSOP (0.65mm pitch AK4563A 23 Top 22 View ...

Page 4

ASAHI KASEI No. Pin Name I/O 1 LOUT O Lch Analog Output Pin 2 ROUT O Rch Analog Output Pin 3 INTL1 I Lch INT #1 Input Pin 4 INTR1 I Rch INT #1 Input Pin 5 INTL0 I Lch ...

Page 5

ASAHI KASEI (AGND, DGND=0V; Note 1) Parameter Power Supply Analog (VA pin) Digital 1 (VD pin) Digital 2 (VT pin) | DGND – AGND | (Note 2) Input Current, Any Pin Except Supplies Analog Input Voltage INTL1-0, INTR1-0, EXTL, EXTR, ...

Page 6

ASAHI KASEI (Ta=25°C; VA, VD, VT=2.5V; fs=48kHz; Signal Frequency =1kHz; Measurement frequency = 10Hz ∼ 20kHz; S/(N+D), D-Range and S/N are value against Full-scale; Unless otherwise specified) Parameter Input PGA Characteristics (IPGA): Input Voltage (INTL1-0, INTR1-0, EXTL, EXTR, LIN, RIN ...

Page 7

ASAHI KASEI (Ta=25°C; VA, VD=2.3 ∼ 3.0V; VT=1.5∼ 3.0V; fs=48kHz; De-emphasis = OFF) Parameter ADC Digital Filter (Decimation LPF): ±0.1dB Passband (Note 10) -1.0dB -3.0dB Stopband (Note 10) Passband Ripple Stopband Attenuation Group Delay (Note 11) Group Delay Distortion ADC ...

Page 8

ASAHI KASEI (Ta=25°C; VA, VD=2.3 ∼ 3.0V, VT=1.5 ∼ 3.0V; C Parameter Control Clock Frequency Master Clock(MCLK) 256fs: Frequency Pulse Width Low Pulse Width High 384fs: Frequency Pulse Width Low Pulse Width High Channel Selection Clock (LRCK) frequency Duty Audio ...

Page 9

ASAHI KASEI Timing Diagram LRCK BCLK SDTO0,1 SDTI Figure 2. Audio Data Input/Output Timing (Audio I/F Format: No.0) CSN tCSS CCLK CDTI CDTO Figure 3. WRITE/READ Command Input Timing CSN CCLK CDTI D4 CDTO MS0067-E-02 tBLR tBLKH tDLR D15 (MSB) ...

Page 10

ASAHI KASEI CSN CCLK A3 CDTI Hi-Z CDTO CSN CCLK CDTI CDTO D4 PDN SDTO0,1 MS0067-E-02 tCKH2 A4 tDCD D0 D1 Figure 5. READ Data Output Timing 1 tCSH Figure 6. READ Data Input Timing 2 tPDW ...

Page 11

ASAHI KASEI System Clock Input The clocks which are required to operate are MCLK (256fs/384fs), LRCK (fs) and BCLK (32fs∼). The master clock (MCLK) should be synchronized with LRCK but the phase is free of care. The MCLK can be ...

Page 12

ASAHI KASEI Power Supply PDN pin PDN pin may be “L” at power-up. ADC Internal PD State AIN SDTO0,1 DAC Internal PD State SDTI AOUT (4) Control register INIT-1 W rite to register Inhibit-1 Read from register Inhibit-1 External clocks ...

Page 13

ASAHI KASEI Digital High Pass Filter (HPF) The ADC has HPF for the DC offset cancel. The cut-off frequency of HPF is 3.7Hz (@fs=48kHz) and it is -0.15dB at 20Hz. It also scales with the sampling frequency (fs). Audio Serial ...

Page 14

ASAHI KASEI LRCK BCLK(32fs) SDTO0,1( SDTI( BCLK(64fs) SDTO0,1( SDTI( 15:MSB, 0:LSB Lch Data LRCK 0 ...

Page 15

ASAHI KASEI Control Register R/W Timing The data on the 4 wires serial interface consists of op-code (3bit), address (LSB-first, 5bit) and control data (LSB-first, 8bit). The transmitting data is output to each bit by “↓” of CCLK, the receiving ...

Page 16

ASAHI KASEI Register Map Addr Register Name 00H Input Select 01H Power Management 02H Mode Control 03H Timer Select FDTM1 04H ALC Mode Control 1 05H ALC Mode Control 2 06H Operation Mode 07H Input PGA Control 08H Peak Hold ...

Page 17

ASAHI KASEI Addr Register Name 01H Power Management R/W RESET PM5-0: Power Management (0: Power down, 1: Power up) PM1-0: IPGA and ALC circuit power control. After exiting PM1-0 = “00”, IPGA goes reset value. (refer to “Operation of IPGA” ...

Page 18

ASAHI KASEI PM4: Power control of DAC PM5: Used both as power control of analog loopback circuit and as selection of MUX. (0: DAC, 1: Analog loopback) When PM5 goes “1”, input for output-AMP is selected to analog loopback circuit ...

Page 19

ASAHI KASEI Organization of Power Management bit PM1-0 IPGA0 ALC IPGA1 ALC 1) All Power PM0: 1 PM1: 1 PM2: 1 PM3: 1 PM4: 1 PM5 2ch REC Mode PM0: 1 PM1: 0 PM2: 1 PM3: 0 PM4: ...

Page 20

ASAHI KASEI Addr Register Name 02H Mode Control R/W RESET DEM1-0: Select De-emphasis frequency The AK4563A includes the digital de-emphasis filter (tc = 50/15µs) by IIR filter. The filter corresponds to three sampling frequencies (32kHz, 44,1kHz and 48kHz). The de-emphasis ...

Page 21

ASAHI KASEI Addr Register Name 03H Timer Select FDTM1 R/W RESET LTM1-0: ALC Limiter Period The IPGA value is changed immediately. When the IPGA value is changed continuously, the change is done by the period specified by LTM1-0 bit. These ...

Page 22

ASAHI KASEI FDTM1-0: FADEIN/OUT Period Setting The FADEIN/OUT operation is done by a period set by FDTM1-0 bits when FDIN or FDOUT bits are set “1”. When IPGA of each L/R channel do zero crossing or timeout independently, the IPGA ...

Page 23

ASAHI KASEI Addr Register Name 04H ALC Mode Control 1 R/W RESET LMTH: Auto Limiter Detection Level / Auto Recovery Waiting Counter Reset Level LMTH ALC Limiter Detection Level ADC Input ≥ –4.0dB 0 ADC Input ≥ –2.0dB 1 Table ...

Page 24

ASAHI KASEI Addr Register Name 05H ALC Mode Control 2 R/W RESET REF6-0: Set the Reference value at ALC Recovery Operation During the ALC recovery operation, when IPGA value becomes the reference value set by REF6-0, the gain of the ...

Page 25

ASAHI KASEI Addr Register Name 06H Operation Mode R/W RESET ALC: ALC Enable Flag 0: ALC Disable (RESET) 1: ALC Enable FDOUT: FADEOUT Enable Flag 0: FADEOUT Disable (RESET) 1: FADEOUT Enable FDIN: FADEIN Enable Flag 0: FADEIN Disable (RESET) ...

Page 26

ASAHI KASEI Addr Register Name 07H Input PGA Control R/W RESET IPGA6-0: Input Analog PGA; 97 levels; Commonly Lch and Rch of IPGA0 and IPGA1. The IPGA value should be the same or smaller than REF value before the ALC1 ...

Page 27

ASAHI KASEI Operation of IPGA [Reading operation] When the IPGA value is read by µP, the IPGA value is the written value finally. Therefore, the actual value may differ to the IPGA value which is read by µP. [Writing operation ...

Page 28

ASAHI KASEI Addr Register Name 08H Lch Peak Hold PHL7 09H Rch Peak Hold PHR7 R/W RESET PHL7-0: Lch Peak Hold (Absolute Value) PHR7-0: Rch Peak Hold (Absolute Value) The peak data is output from ADC0 held L/R ...

Page 29

ASAHI KASEI ALC Operation 1. ALC Limiter Operation During the ALC limiter operation, when either Lch or Rch in IPGA0 and IPGA1 exceed ALC limiter detection level (LMTH), IPGA value is attenuated by ALC limiter ATT step (LMAT1-0) automatically. Then ...

Page 30

ASAHI KASEI (3) Zero crossing timeout (ZTM1-0) Limiter detection level (LMTH) Recovery waiting counter reset level (LMTH) Limiter detection level (LMTH) Figure 17. In case of continuing the limiter operation (ZELMN = “0”) (1) When the input level exceeds the ...

Page 31

ASAHI KASEI 2. ALC Recovery Operation The ALC recovery operation waits until a time of setting WTM1-0 bits after completing the ALC limiter. If the input signal does not exceed “ALC recovery waiting counter reset level (LMTH)”, the ALC recovery ...

Page 32

ASAHI KASEI (1) Recovery waiting counter reset level (LMTH) or reference value of recovery operation (REF6-0) Zero Crossing Detect (2) Zero crossing timeout (ZTM1-0) & Recovery waiting time (WTM1-0) (1) When the input signal exceeds the ALC recovery waiting counter ...

Page 33

ASAHI KASEI Does not change the following registers during the ALC operation. • LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RATT, REF6-0, ZELMN WR (Power Management Control & Signal Select registers) WR (ZTM1-0, WTM1-0, LTM1- Finish ALC-Mode and become manual-Mode ...

Page 34

ASAHI KASEI FADEIN Mode In FADEIN Mode, the IPGA value is increased at the value set by FDATT when FDIN bit changes from “0” to “1”. The update period can be set by FDTM1-0 bits. The FADEIN Mode is always ...

Page 35

ASAHI KASEI FADEOUT Mode In FADEOUT mode, the present IPGA value is decreased until the MUTE state when FDOUT bit changes from “0” to “1”. This operation is always detected by the zero crossing operation. If the large signal is ...

Page 36

ASAHI KASEI Figure 23 shows the system connection diagram. An evaluation board (AKD4563A) is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results 0.1 µ ...

Page 37

ASAHI KASEI 1. Grounding and Power Supply Decoupling The AK4563A requires careful attention to power supply and grounding arrangements usually supplied from analog supply in system and VD is supplied from analog supply in system via a resistor ...

Page 38

ASAHI KASEI 28pin VSOP (Unit: mm) 9.8±0.2 0.65 +0.10 0.22 -0.05 0.12 M *1: Dimension does not include mold flash. Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS0067-E-02 PACKAGE 15 ...

Page 39

... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0067-E-02 MARKING AKM AK4563AVF XXXBYYYYC XXXBYYYYC data code identifier XXXB : Lot number (X : Digit number Alpha character) YYYYC : Assembly date (Y : Digit number, C Alpha character) ...

Related keywords