VT82C686B

Manufacturer Part NumberVT82C686B
ManufacturerETC-unknow
VT82C686B datasheet
 


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Offset 41 –Hardware Monitor Interrupt Status 1 ........... RO
7
Fan 2 Error
0
No error ..................................................default
1
Fan 2 count limit exceeded
6
Fan 1 Error
0
No error ..................................................default
1
Fan 1 count limit exceeded
........................................ always reads 0
5
Reserved
4
TSENS1 Temperature Error
0
No error ..................................................default
1
High or low hot temperature limit exceeded.
The
interrupt
mode
Temperature Resolution register Rx4B[1-0].
3
VSENS3 Voltage Error (5V)
0
No error ..................................................default
1
High or low limit exceeded
2
Internal Core VCC Voltage Error (3.3V)
0
No error ..................................................default
1
High or low limit exceeded
1
VSENS2 Voltage Error (2.5V NB Core Voltage)
0
No error ..................................................default
1
High or low limit exceeded
0
VSENS1 Voltage Error (2.0V CPU Core Voltage)
0
No error ..................................................default
1
High or low limit exceeded
Offset 42 –Hardware Monitor Interrupt Status 2 ........... RO
7
TSENS3 (Internal Bandgap) Temp Error
0
No error ..................................................default
1
High or low hot temperature limit exceeded.
Interrupt mode is determined by Rx4B[5-4].
6-5
Reserved
........................................ always reads 0
4
Chassis Error
0
No error ..................................................default
1
Chassis Intrusion has gone high
3
TSENS2 Temperature Error
0
No error ..................................................default
1
High or low hot temperature limit exceeded.
Interrupt mode is determined by Rx4B[3-2].
2-1
Reserved
........................................ always reads 0
0
VSENS4 Voltage Error (12V)
0
No error ..................................................default
1
High or low limit exceeded
Note: When either status register is read, status conditions in
that register are reset.
In the case of voltage priority
indications, if two or more voltages were out of limits, then
another indication would automatically be generated if it was
not handled during interrupt service. Errant voltages may be
disabled in the control register until the operator has time to
clear the errant condition or set the limit higher or lower.
Revision 1.71 June 9, 2000
Offset 43 –Hardware Monitor Interrupt Mask 1 .......... RW
7
Fan 2 Count Error Mask
6
Fan 1 Count Error Mask
5
TSENS1 Thermal Alarm Control Mask
4
TSENS1 Temperature Error Mask
is
determined
by
3
VSENS3 Voltage Error Mask (5V)
2
Internal Core VCC Voltage Error Mask (3.3V)
1
VSENS2 Voltage Error Mask (2.5V NB Core)
0
VSENS1 Voltage Error Mask (2.0V CPU Core)
Offset 44 –Hardware Monitor Interrupt Mask 2 .......... RW
7
TSENS3 Temperature Error Mask
6
TSENS3 Thermal Alarm Control Mask
5
TSENS2 Thermal Alarm Control Mask
4
Chassis Error Mask
3
TSENS2 Temperature Error Mask
2-1
Reserved
0
VSENS4 Voltage Error Mask (12V)
-104-
VT82C686B
0
Enable interrupt on error status bit set ......... def
1
Disable interrupt on error status bit set
0
Enable interrupt on error status bit set ......... def
1
Disable interrupt on error status bit set
0
Enable TSENS1 over-temp condition to
control the thermal alarm (function 4 Rx40[7]
automatic CPU clock throttling must be set )def
1
Disable
0
Enable interrupt on error status bit set ......... def
1
Disable interrupt on error status bit set
0
Enable interrupt on error status bit set ......... def
1
Disable interrupt on error status bit set
0
Enable interrupt on error status bit set ......... def
1
Disable interrupt on error status bit set
0
Enable interrupt on error status bit set ......... def
1
Disable interrupt on error status bit set
0
Enable interrupt on error status bit set ......... def
1
Disable interrupt on error status bit set
0
Enable interrupt on error status bit set ......... def
1
Disable interrupt on error status bit set
0
Enable TSENS3 over-temp condition to
control the thermal alarm (function 4 Rx40[7]
automatic CPU clock throttling must be set) def
1
Disable
0
Enable TSENS2 over-temp condition to
control the thermal alarm (function 4 Rx40[7]
automatic CPU clock throttling must be set) def
1
Disable
0
Enable interrupt on error status bit set ......... def
1
Disable interrupt on error status bit set
0
Enable interrupt on error status bit set ......... def
1
Disable interrupt on error status bit set
........................................always reads 0
0
Enable interrupt on error status bit set ......... def
1
Disable interrupt on error status bit set
Hardware Monitor I/O Space Registers