VT82C686B

Manufacturer Part NumberVT82C686B
ManufacturerETC-unknow
VT82C686B datasheet
 


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
Page 71
72
Page 72
73
Page 73
74
Page 74
75
Page 75
76
Page 76
77
Page 77
78
Page 78
79
Page 79
80
Page 80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Page 77/128

Download datasheet (2Mb)Embed
PrevNext
7HFKQRORJLHV ,QF
Offset 4B-48 - Drive Timing Control (A8A8A8A8h) ...... RW
The following fields define the Active Pulse Width and
Recovery Time for the IDE DIOR# and DIOW# signals:
31-28 Primary Drive 0 Active Pulse Width ...... def=1010b
27-24 Primary Drive 0 Recovery Time ............. def=1000b
23-20 Primary Drive 1 Active Pulse Width ...... def=1010b
19-16 Primary Drive 1 Recovery Time ............. def=1000b
15-12 Secondary Drive 0 Active Pulse Width .. def=1010b
11-8 Secondary Drive 0 Recovery Time ......... def=1000b
Secondary Drive 1 Active Pulse Width .. def=1010b
7-4
3-0
Secondary Drive 1 Recovery Time ......... def=1000b
The actual value for each field is the encoded value in the field
plus one and indicates the number of PCI clocks.
Offset 4C - Address Setup Time (FFh) ............................ RW
7-6
Primary Drive 0 Address Setup Time ........ def = 11
5-4
Primary Drive 1 Address Setup Time ....... def = 11
3-2
Secondary Drive 0 Address Setup Time .... def = 11
1-0
Secondary Drive 1 Address Setup Time .... def = 11
For each field above:
00 1T
01 2T
10 3T
11 4T
.....................................................default
Revision 1.71 June 9, 2000
Offset 53-50 - UltraDMA Extended Timing Control ..... RW
31
Pri Drive 0 UltraDMA-Mode Enable Method
0
Enable by using “Set Feature” command..... def
1
Enable by setting bit-30 of this register
30
Pri Drive 0 UltraDMA-Mode Enable
0
Disable................................................... default
1
Enable UltraDMA-Mode Operation
29
Pri Drive 0 Transfer Mode
0
DMA or PIO Mode ............................... default
1
UltraDMA Mode
28
Pri Drive 0 Cabal Type Reporting
0
Disable................................................... default
1
Enable
27
Reserved
........................................always reads 0
26-24 Pri Drive 0 Cycle Time (T = 10nsec)
000 2T
001 3T
010 4T
011 5T
100 6T
101 7T
110 8T
111 9T
.................................................... default
23
Pri Drive 1 UltraDMA-Mode Enable Method
22
Pri Drive 1 UltraDMA-Mode Enable
21
Pri Drive 1 Transfer Mode
20
Pri Drive 1 Cabal Type Reporting
0
Disable................................................... default
1
Enable
19
Reserved
........................................always reads 0
18-16 Pri Drive 1 Cycle Time.......... (see above for default)
15
Sec Drive 0 UltraDMA-Mode Enable Method
14
Sec Drive 0 UltraDMA-Mode Enable
13
Sec Drive 0 Transfer Mode
12
Sec Drive 0 Cabal Type Reporting
0
Disable................................................... default
1
Enable
11
Reserved
........................................always reads 0
10-8 Sec Drive 0 Cycle Time ......... (see above for default)
7
Sec Drive 1 UltraDMA-Mode Enable Method
6
Sec Drive 1 UltraDMA-Mode Enable
5
Sec Drive 1 Transfer Mode
4
Sec Drive 1 Cabal Type Reporting
0
Disable................................................... default
1
Enable
3
Reserved
........................................always reads 0
2-0
Sec Drive 1 Cycle Time ......... (see above for default)
Each byte defines UltraDMA operation for the indicated drive.
The bit definitions are the same within each byte.
-71-
Function 1 Registers - Enhanced IDE Controller
VT82C686B