SAK-XC167CI-16F40F Infineon(siemens), SAK-XC167CI-16F40F Datasheet
SAK-XC167CI-16F40F
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SAK-XC167CI-16F40F Summary of contents
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... XC1 She ...
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Edition 2002-10 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2002. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms ...
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XC1 ...
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XC167 Preliminary Revision History: 2002-10 Previous Version: --- Page Subjects (major changes since last revision) Controller Area Network (CAN): License of Robert Bosch GmbH We Listen to Your Comments Any information within this document that you feel is wrong, unclear ...
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Preliminary 16-Bit Single-Chip Microcontroller XC166 Family XC167 1 Summary of Features • High Performance 16-bit CPU with 5-Stage Pipeline – Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution) – 1-Cycle Multiplication (16 – 1-Cycle Multiply-and-Accumulate (MAC) ...
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Preliminary • Mbytes External Address Space for Code and Data – Programmable External Bus Characteristics for Different Address Ranges – Multiplexed or Demultiplexed External Address/Data Buses – Selectable Address Bus Width – 16-Bit or 8-Bit Data Bus ...
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... Preliminary Table 1 XC167 Derivative Synopsis 1) Derivative Program Memory On-Chip RAM SAK-XC167CI-16F40F, 128 Kbytes Flash SAK-XC167CI-16F20F SAF-XC167CI-16F40F, 128 Kbytes Flash SAF-XC167CI-16F20F SAB-XC167CI-16F40F, 128 Kbytes Flash SAB-XC167CI-16F20F (on request) 1) This Data Sheet is valid for devices starting with and including design step AC. Data Sheet Summary of Features ...
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Preliminary 2 General Device Information 2.1 Introduction The XC167 derivatives are high-performance members of the Infineon XC166 Family of full featured single-chip CMOS microcontrollers. These devices extend the functionality and performance of the C166 Family in terms of instructions (MAC ...
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Preliminary 2.2 Pin Configuration and Definition The pins of the XC167 are described in detail in functions. Figure 2 summarizes all pins in a condensed way, showing their location on the 4 sides of the package. E*) and C*) mark ...
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Preliminary Table 2 Pin Definitions and Functions Symbol Pin Input Function Num. Outp. P20. For details, please refer to the description of P20. NMI 4 I Non-Maskable Interrupt Input. A high to low transition at this pin causes ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Function Num. Outp Port 4-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Function Num. Outp Port 6-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Function Num. Outp Port 16-bit input-only port. The pins of Port 5 also serve as analog input channels for the A/D converter, or they ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Function Num. Outp Port 8-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Function Num. Outp Port 15-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Function Num. Outp Port 8-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Function Num. Outp. P20 IO Port 6-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output. The input ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Function Num. Outp. PORT0 IO PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. Each pin can be programmed for input (output driver in high-impedance state) ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Function Num. Outp. PORT1 IO continued (cont’d) P1H.0 127 I CC6POS0 CAPCOM6: Position 0 Input, I EX0IN I/O CC23IO P1H.1 128 I CC6POS1 CAPCOM6: Position 1 Input, I/O MRST1 ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Function Num. Outp. RSTIN 142 I Reset Input with Schmitt-Trigger characteristics. A low level at this pin while the oscillator is running resets the XC167. An internal pullup resistor ...
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Preliminary 3 Functional Description The architecture of the XC167 combines advantages of RISC, CISC, and DSP processors with an advanced peripheral subsystem in a very well-balanced way. In addition, the on-chip memory blocks allow the design of compact systems-on-silicon with ...
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Preliminary 3.1 Memory Subsystem and Organization The memory space of the XC167 is configured in a Von Neumann architecture, which means that all internal and external resources, such as code memory, data memory, registers and I/O ports, are organized within ...
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Preliminary so-called General Purpose Registers (GPRs). The upper 256 bytes of the DPRAM are directly bitaddressable. When used by a GPR, any location in the DPRAM is bitaddressable. 1024 bytes (2 512 bytes) of the address space are reserved for ...
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Preliminary 3.2 External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required one of ...
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Preliminary The EBC also controls accesses to resources connected to the on-chip LXBus. The LXBus is an internal representation of the external bus and allows accessing integrated peripherals and modules in the same way as external components. The TwinCAN module ...
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Preliminary the number of bits to be shifted. Also multiplication and most MAC instructions execute in one single cycle. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: for example, a 32-/16-bit division ...
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Preliminary 3.4 Interrupt System With an interrupt response time of typically 8 CPU clocks (in case of internal program execution), the XC167 is capable of reacting very fast to the occurrence of non- deterministic events. The architecture of the XC167 ...
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Preliminary Table 4 XC167 Interrupt Nodes Source of Interrupt or PEC Service Request CAPCOM Register 0 CAPCOM Register 1 CAPCOM Register 2 CAPCOM Register 3 CAPCOM Register 4 CAPCOM Register 5 CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 ...
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Preliminary Table 4 XC167 Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request CAPCOM Register 30 CAPCOM Register 31 CAPCOM Timer 0 CAPCOM Timer 1 CAPCOM Timer 7 CAPCOM Timer 8 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer ...
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Preliminary Table 4 XC167 Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request End of PEC Subch. CAPCOM6 Timer T12 CAPCOM6 Timer T13 CAPCOM6 Emergency CAPCOM6 SSC1 Transmit SSC1 Receive SSC1 Error CAN0 CAN1 CAN2 CAN3 CAN4 CAN5 CAN6 ...
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Preliminary The XC167 also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching ...
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Preliminary 3.5 On-Chip Debug Support (OCDS) The On-Chip Debug Support system provides a broad range of debug and emulation features built into the XC167. The user software running on the XC167 can thus be debugged within the target system environment. ...
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Preliminary 3.6 Capture/Compare Units (CAPCOM1/2) The CAPCOM units support generation and control of timing sequences channels with a maximum resolution of 1 system clock cycle (8 cycles in staggered mode). The CAPCOM units are typically used ...
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Preliminary When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (‘captured’) into the capture/compare register in response to an external event at the port pin which is associated with ...
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Preliminary 3.7 The Capture/Compare Unit CAPCOM6 The CAPCOM6 unit supports generation and control of timing sequences three 16-bit capture/compare channels plus one independent 10-bit compare channel. In compare mode the CAPCOM6 unit provides two output signals per ...
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Preliminary 3.8 General Purpose Timer (GPT12E) Unit The GPT12E unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse ...
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Preliminary SYS T2IN Control T2EUD SYS T3IN Control T3EUD SYS T4IN Control T4EUD … 12 Figure 7 Block Diagram of GPT1 With ...
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Preliminary after the capture procedure. This allows the XC167 to measure absolute time differences or to perform pulse multiplication without software overhead. The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3’s inputs ...
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Preliminary 3.9 Real Time Clock The Real Time Clock (RTC) module of the XC167 is directly clocked via a separate clock driver with the on-chip auxiliary oscillator frequency ( independent from the selected clock generation mode of the XC167. The ...
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Preliminary The RTC module can be used for different purposes: • System clock to determine the current time and date, optionally during idle mode, sleep mode, and power down mode • Cyclic time based interrupt, to provide a system time ...
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Preliminary 3.10 A/D Converter For analog signal measurement, a 10-bit A/D converter with 16 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the ...
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Preliminary 3.11 Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1) The Asynchronous/Synchronous Serial Interfaces ASC0/ASC1 (USARTs) provide serial communication with other microcontrollers, processors, terminals or external peripheral components. They are upward compatible with the serial ports of the Infineon 8-bit microcontroller families and support ...
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Preliminary 3.12 High Speed Synchronous Serial Channels (SSC0/SSC1) The High Speed Synchronous Serial Channels SSC0/SSC1 support full-duplex and half- duplex synchronous communication. It may be configured so it interfaces with serially linked peripheral components, full SPI functionality is supported. A ...
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Preliminary 3.13 TwinCAN Module The integrated TwinCAN module handles the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2.0 part B (active), i.e. the on-chip TwinCAN module can receive and transmit standard frames with ...
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Preliminary Summary of Features • CAN functionality according to CAN specification V2.0 B active. • Data transfer rate Mbit/s • Flexible and powerful message transfer control and error handling capabilities • Full-CAN functionality and Basic CAN functionality ...
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Preliminary 3.15 Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, ...
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Preliminary 3.16 Clock Generation The Clock Generation Unit uses a programmable on-chip PLL with multiple prescalers to generate the clock signals for the XC167 with high flexibility. The master clock the reference clock signal, and is used for TwinCAN and ...
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Preliminary Table 7 Summary of the XC167’s Parallel Ports Port Control PORT0 Pad drivers PORT1 Pad drivers Port 2 Pad drivers, Open drain, Input threshold Port 3 Pad drivers, Open drain, Input threshold Port 4 Pad drivers, Open drain, Input ...
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Preliminary 3.18 Power Management The XC167 provides several means to control the power it consumes either at a given time or averaged over a certain timespan. Three mechanisms can be used (partly in parallel): • Power Saving Modes switch the ...
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Preliminary 3.19 Instruction Set Summary Table 8 lists the instructions of the XC167 in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, ...
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Preliminary Table 8 Instruction Set Summary (cont’d) Mnemonic Description JMPA/I/R Jump absolute/indirect/relative if condition is met JMPS Jump absolute to a code segment JB(C) Jump relative if direct bit is set (and clear bit) JNB(S) Jump relative if direct bit ...
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Preliminary 4 Electrical Parameters 4.1 Absolute Maximum Ratings Table 9 Absolute Maximum Rating Parameters Parameter Symbol Storage temperature T Junction temperature T Voltage on V pins with V DDI V respect to ground ( ) Voltage on ...
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... DDP DDI V Reference voltage 2)3) mA Per IO pin mA Per analog input 2)3) pin – I > – I < – > – < Pin drivers in 5) default mode C SAB-XC167… C SAF-XC167… C SAK-XC167… < 0). The absolute sum OV V1.0, 2002-10 ...
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Preliminary 4) An overload current ( I ) through a pin injects a certain error current ( OV current adds to the respective pin’s leakage current ( current and is defined by the overload coupling factor compared to the polarity ...
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Preliminary 4.5 DC Parameters DC Characteristics 1) (Operating Conditions apply) Parameter Input low voltage TTL (all except XTAL1, XTAL3) Input low voltage for XTAL1, XTAL3 Input low voltage (Special Threshold) Input high voltage TTL (all except XTAL1, XTAL3) Input high ...
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Preliminary DC Characteristics (cont’d) 1) (Operating Conditions apply) Parameter 10) Level inactive hold current 10) Level active hold current XTAL1, XTAL3 input current 11) Pin capacitance (digital inputs/outputs) 1) Keeping signal levels within the limits specified in this table, ensures ...
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Preliminary Table 12 Current Limits for Port Output Drivers Port Output Driver Maximum Output Current Mode ( I OLmax Strong driver 10 mA Medium driver 4.0 mA Weak driver 0 output current above | I | may ...
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Preliminary I [mA] 140 120 100 Figure 11 Supply/Idle Current as a Function of Operating Frequency Data Sheet XC167 Derivatives Electrical Parameters I DDImax I DDItyp I IDXmax I IDXtyp f ...
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Preliminary I PDO [ A] 1500 1000 500 -50 0 Figure 12 Sleep and Power Down Supply Current as a Function of Temperature Data Sheet Electrical Parameters 50 100 150 55 XC167 Derivatives T [°C] J V1.0, 2002-10 ...
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Preliminary 4.6 A/D Converter Characteristics Table 13 A/D Converter Characteristics (Operating Conditions apply) Parameter Analog reference supply Analog reference ground Analog input voltage range Basic clock frequency 4) Conversion time Calibration time after reset Total unadjusted error Total capacitance of ...
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Preliminary 2) V may exceed AIN AGND AREF these cases will be X000 or X3FF The limit values for must not be exceeded when selecting the peripheral frequency and the ADCTC setting ...
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Preliminary Sample time and conversion time of the XC167’s A/D Converter are programmable. In compatibility mode, the above timing can be calculated using f The limit values for must not be exceeded when selecting ADCTC. BC Table 14 A/D Converter ...
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Preliminary 5 Timing Parameters 5.1 Definition of Internal Timing The internal operation of the XC167 is controlled by the internal master clock f The master clock signal can be generated from the oscillator clock signal MC different mechanisms. The duration ...
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Preliminary Bypass Operation When bypass operation is configured (PLLCTRL = 0x the internal oscillator (input clock signal XTAL1) through the input- and output- prescalers ((PLLIDIV+1) (PLLODIV+1)). MC OSC If both divider factors are selected as ’1’ ...
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Preliminary N For a period of TCM the accumulated PLL jitter is defined by the corresponding deviation [ns] = (1 So, for a period of 3 TCMs @ 20 MHz ...
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Preliminary 5.2 External Clock Drive XTAL1 Table 16 External Clock Drive Characteristics (Operating Conditions apply) Parameter Oscillator period 2) High time 2) Low time 2) Rise time 2) Fall time 1) The maximum limit is only relevant for PLL operation ...
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Preliminary 5.3 Testing Waveforms 2.0 V 0.8 V 0.45 V Figure 17 Input Output Waveforms V + 0.1 V Load V - 0.1 V Load For timing purposes a port pin is no longer floating when a 100 mV change ...
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Preliminary 5.4 AC Characteristics Table 17 CLKOUT Reference Signal Parameter CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time 1) The CLKOUT cycle time is influenced by the PLL jitter (given values apply to ...
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Preliminary Variable Memory Cycles External bus cycles of the XC167 are executed in five subsequent cycle phases (AB F). The duration of each cycle phase is programmable (via the TCONCSx registers) to adapt the external bus cycles ...
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Preliminary Table 19 External Bus Cycle Timing (Operating Conditions apply) Parameter Output valid delay for: RD, WR(L/H) Output valid delay for: A23 A16, BHE, ALE Output valid delay for: A15 A0 (on PORT1) Output valid delay for: A15 A0 (on ...
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Preliminary tp AB CLKOUT tc 11 ALE tc | A23-A16, BHE, CSx RD WR(L/ AD15-AD0 Low Address (read AD15-AD0 Low Address (write) Figure 20 Multiplexed Bus Cycle Data Sheet ...
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Preliminary tp AB CLKOUT tc 11 ALE tc | A23-A0, BHE, CSx RD WR(L/H) D15-D0 (read) D15-D0 (write) Figure 21 Demultiplexed Bus Cycle Data Sheet Address ...
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Preliminary Bus Cycle Control via READY Input The duration of an external bus cycle can be controlled by the external circuitry via the READY input signal. The polarity of this input signal can be selected. Synchronous READY permits the shortest ...
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Preliminary tp D CLKOUT RD, WR D15-D0 (read) D15-D0 (write) READY Synchronous READY Asynchron. Figure 22 READY Timing Note: If the READY input is sampled inactive at the indicated sampling point (“Not Rdy”) a READY-controlled waitstate is inserted ( sampling ...
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Preliminary External Bus Arbitration Table 20 Bus Arbitration Timing (Operating Conditions apply) Parameter Input setup time for: HOLD input Output delay rising edge for: HLDA, BREQ Output delay falling edge for: HLDA Data Sheet Timing Parameters Symbol Limits min. tc ...
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Preliminary CLKOUT tc 40 HOLD HLDA BREQ CSx, RD, WR(L/H) Addr, Data, BHE Figure 23 External Bus Arbitration, Releasing the Bus Notes 1) The XC167 will complete the currently running bus cycle before granting bus access. 2) This is the ...
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Preliminary CLKOUT HOLD HLDA BREQ CSx, RD, WR(L/H) Addr, Data, BHE Figure 24 External Bus Arbitration, (Regaining the Bus) Notes 1) This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the ...
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Preliminary 6 Packaging P-TQFP-144-19 (Plastic Metric Quad Flat Package) 0.5 17.5 2) 0.22 ±0.05 0.08 A 144 1 Index Marking 1) Does not include plastic or metal protrusion of 0.25 max. per side 2) ...
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Published by Infineon Technologies AG ...