21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 

Specifications of 21150-AB

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15.1.19
Memory Base Address Register—Offset 20h
This section describes the memory base address register.
This register must be initialized by configuration software.
Dword address = 20h
Byte enable p_cbe_l<3:0> = xx00b
Dword Bit
3:0
Reserved
Memory base address
15:4
<31:20>
15.1.20
Memory Limit Address Register—Offset 22h
This section describes the memory limit address register.
This register must be initialized by configuration software.
Dword address = 20h
Byte enable p_cbe_l<3:0> = 00xxb
Dword Bit
19:16
Reserved
Memory limit address
31:20
<31:20>
15.1.21
Prefetchable Memory Base Address Register—Offset 24h
This section describes the prefetchable memory base address register.
This register must be initialized by configuration software.
Dword address = 24h
Byte enable p_cbe_l<3:0> = xx00b
Preliminary
Datasheet
Name
R/W
The low 4 bits of this register are read only and
R
return 0.
Defines the bottom address of an address
range used by the 21150 to determine when to
forward memory transactions from one
interface to the other. The upper 12 bits are
writable and correspond to address bits
R/W
<31:20>. The lower 20 bits of the address are
assumed to be 0. The memory address range
adheres to 1MB alignment and granularity.
Reset value: 0.
Name
R/W
The low 4 bits of this register are read only and
R
return 0.
Defines the top address of an address range
used by the 21150 to determine when to
forward memory transactions from one
interface to the other. The upper 12 bits are
writable and correspond to address bits
R/W
<31:20>. The lower 20 bits of the address are
assumed to be FFFFFh. The memory address
range adheres to 1MB alignment and
granularity.
Reset value: 0.
21150
Description
Description
115