21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 

Specifications of 21150-AB

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Dword Bit
8
Chip reset
10:9
Test mode
15:11
Reserved
15.2.3
Arbiter Control Register—Offset 42h
This section describes the arbiter control register.
Dword address = 40h
Byte enablep_cbe_l<3:0> = 00xxb
Dword Bit
25:16
Arbiter control
31:26
Reserved
Preliminary
Datasheet
Name
R/W
Chip and secondary bus reset control.
When 1—Causes the 21150 to perform a chip
reset. Data buffers, configuration registers, and
both the primary and secondary interfaces are
reset to their initial state.
The 21150 clears this bit once chip reset is
complete. The 21150 can then be
R/W1TR
reconfigured.
Secondary bus reset s_rst_l is asserted and
the secondary reset bit in the bridge control
register is set when this bit is set. The
secondary reset bit in the bridge control
register must be cleared in order to deassert
s_rst_l.
Controls the testability of the 21150’s internal
counters. These bits are used for chip test only.
The value of these bits controls which bytes of
the counters are exercised:
• 00b = Normal functionality—all bits are
R/W
exercised.
• 01b = Byte 1 is exercised.
• 10b = Byte 2 is exercised.
• 11b = Byte 0 is exercised.
Reset value: 00b.
R
Reserved. Returns 0 when read.
Name
R/W
Each bit controls whether a secondary bus
master is assigned to the high priority arbiter
group or the low priority arbiter group. Bits
<24:16> correspond to request inputs
s_req_l<8:0>, respectively. Bit <25>
corresponds to the 21150 as a secondary bus
R/W
master.
When 0—Indicates that the master belongs to
the low priority group.
When 1—Indicates that the master belongs to
the high priority group.
Reset value: 10 0000 0000b.
R
Reserved. Returns 0 when read.
21150
Description
Description
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