RJ80530KZ933512

Manufacturer Part NumberRJ80530KZ933512
DescriptionLow Voltage Pentium III Processor with 512 kB L2 Cache
ManufacturerIntel Corporation
RJ80530KZ933512 datasheet
 


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Table 33. Signal Description (Sheet 3 of 8)
Name
Type
BR0#
I/O
BR1#
I
BSEL[1:0]
O
CLKREF
I
D[63:0]#
I/O
Datasheet
LV Intel
Description
The BR0# and BR1#(Bus Request) balls drive the BREQ[1:0]# signals in the
system. The BREQ[1:0]# signals are interconnected in a rotating manner to
individual processor balls. The following table gives the rotating interconnect
between the processor and bus signals.
BR0# (I/O) and BR1# Signals Rotating Interconnect
Bus Signal
Agent 0 Ball
BREQ0#
BR0#
BREQ1#
BR1#
During power-up configuration, the central agent asserts the BR0# bus signal in the
system to assign the symmetric agent ID to the processor. The processor samples
its BR0# ball on the active-to-inactive transition of the RESET# to obtain its
symmetric agent ID. The processor asserts the BR0# ball to request the system
bus. All agents then configure their balls to match the appropriate bus signal
protocol, as shown in the following table.
BR0# (I/O) and BR1# Signals Rotating Interconnect
Ball Sampled Active in RESET#
BR0#
BR1#
For uniprocessor designs, BR0# must be connected to a 10-56
The BSEL[1:0] (Select Processor System Bus Speed) signals are used to configure
the processor for the system bus frequency. The chipset and system clock
generator also uses the BSEL signals. The VTT_PWRGD signal informs the
processor to output the BSEL signals. During power up the BSEL signals are
indeterminate for a small period of time. The chipset and clock generator should not
sample the BSEL signals until the VTT_PWRGD signal is asserted. The assertion
of the VTT_PWRGD signal indicates that the BSEL signals are stable and driven to
a final state by the processor. Please refer to
between the BSEL and VTT_PWRGD signals.
The following table shows the encoding scheme for BSEL[1:0]. The LV Pentium III
processor 512K supports only a 133 MHz system bus frequency. If another
frequency is used, the processor is not guaranteed to function properly.
BSEL[1:0]
System Bus Frequency
11
In Single-ended clock mode the CLKREF input is a filtered 1.25V supply voltage for
the processor PLL. A voltage divider and decoupling solution is provided by the
®
motherboard. Refer to th e LV Intel
Pentium
Platform Design Guide for i mplementation details.
When the processor operates in differential clock mode, this signal becomes
BCLK#.
The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit
data path between the processor system bus agents, and must connect the
appropriate balls on all such agents. The data driver asserts DRDY# to indicate a
valid data transfer.
®
®
Pentium
III Processor 512K
Agent 1 Ball
BR1#
BR0#
Agent ID
0
3
resistor to V
.
SS
Figure 16
for the timing relationship
133 MHz
®
III Processor 512K Dual Processor
61