AT86RF232 Atmel Corporation, AT86RF232 Datasheet
AT86RF232
Specifications of AT86RF232
Related parts for AT86RF232
AT86RF232 Summary of contents
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... Compliant to IEEE 802.15.4-2011, IEEE 802.15.4-2006 and IEEE 802.15.4-2003 • Compliant to EN 300 328/440, FCC-CFR-47 Part 15, ARIB STD-66, RSS-210 8321A–MCU Wireless–10/11 (LISTEN) (at max. transmit power) AT86RF232 Low Power, 2.4GHz Transceiver for ZigBee, IEEE 802.15.4, 6LoWPAN, RF4CE and ISM Applications AT86RF232 PRELIMINARY Rev. 8321A–MCU Wireless–10/11 1 ...
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... Pin-out Diagram AT86RF232 2 Figure 1-1. Atmel AT86RF232 Pin-out Diagram. 32 AVSS 1 AVSS 2 AVSS 3 RFP 4 RFN 5 AVSS 6 DVSS 7 8 /RST Note: 1. The exposed paddle is electrically connected to the die inside the package. It shall be soldered to the board to ensure electrical and thermal contact and good mechanical stability ...
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... Pin Descriptions Table 1-1. Atmel AT86RF232 Pin Description. Pins Name Type 1 AVSS Ground 2 AVSS Ground 3 AVSS Ground 4 RFP RF I/O 5 RFN RF I/O 6 AVSS Ground 7 DVSS Ground 8 /RST Digital input 9 DIG1 Digital output (Ground) 10 DIG2 Digital output (Ground) 11 SLP_TR Digital input 12 DVSS Ground 13, 14 ...
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... A DC path to ground or supply voltage is not allowed. The RF port DC values depend on the operating state, see state, when the analog front-end is disabled (see pulled to ground, preventing a floating voltage. Figure 1-2. RX LNA Feedback RXTX Chapter Section 7.1.2.3), the RF pins are ® AT86RF232 7. In TRX_OFF 8321A–MCU Wireless–10/11 ...
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... RF pins. XTAL1, XTAL2 The pin 26 (XTAL1) of Atmel AT86RF232 is the input of the reference oscillator amplifier (XOSC), the pin 25 (XTAL2) is the output. A detailed description of the crystal oscillator setup and the related XTAL1/XTAL2 pin configuration can be found in Section 9 ...
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... Driver Strength Settings 1.3.2 Pull-up and Pull-down Configuration AT86RF232 6 The Atmel AT86RF232 provides a digital microcontroller interface. The interface comprises a slave SPI (/SEL, SCLK, MOSI and MISO) and additional control signals (CLKM, IRQ, SLP_TR, /RST and DIG2). The microcontroller interface is described in detail in Chapter 6 ...
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... Wireless sensor networks Residential and commercial automation Health care Consumer electronics PC peripherals The AT86RF232 can be operated by using an external microcontroller like Atmel AVR microcontrollers. A comprehensive software programming description can be found in reference [6], AT86RF232 Software Programming Model. AT86RF232 ® ...
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... The number of external components is minimized such that only the antenna, the crystal and decoupling capacitors are required. The bidirectional differential antenna pins (RFP, RFN) are used for transmission and reception, thus no external antenna switch is needed. The Atmel AT86RF232 block diagram is shown in XOSC AVREG PLL ...
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... An internal 128-byte RAM for RX and TX (Frame Buffer) buffers the data to be transmitted or the received data. The configuration of the Atmel AT86RF232, reading and writing of Frame Buffer is controlled by the SPI interface and additional control lines. The AT86RF232 further contains comprehensive hardware-MAC support (Extended Operating Mode) and a security engine (AES) to improve the overall system power efficiency and timing ...
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... Application Circuits 5.1 Basic Application Schematic AT86RF232 10 A basic application schematic of the Atmel AT86RF232 with a single-ended RF connector is shown in Figure 5-1. The 50Ω single-ended RF input is transformed to the 100Ω differential RF port impedance using balun B1. The capacitors C1 and C2 provide AC coupling of the RF input to the RF port, optional capacitor C4 improves matching if required ...
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... Crosstalk from digital signals on the crystal pins or the RF pins can degrade the system performance. Therefore, a low-pass filter (C3, R1) is placed close to the Atmel AT86RF232 CLKM output pin to reduce the emission of CLKM signal harmonics. This is not needed if the pin 17 (CLKM) is not used as a microcontroller clock source. In that case, the output should be turned off during device initialization ...
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... RX and TX Frame Time Stamping (TX_ARET) Frame Buffer Empty Indicator Dynamic Frame Buffer Protection An extended feature set application schematic illustrating the use of the AT86RF232 Extended Feature Set, see Chapter shows all additional hardware features combined possible to use all features separately or in various combinations ...
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... Wireless–10/11 In this example, a balun (B1) transforms the differential RF signal at the Atmel AT86RF232 radio transceiver RF pins (RFP/RFN single ended RF signal, similar to the Basic Application Schematic; refer to transceiver searches for the most reliable RF signal path using the Antenna Diversity algorithm. One antenna is selected (SW2) by the Antenna Diversity RF switch control ...
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... GPIO4 GPIO5 Microcontrollers with a master SPI such as Atmel AVR family interface directly to the AT86RF232. The SPI is used for register, Frame Buffer, SRAM and AES access. The additional control signals are connected to the GPIO/IRQ interface of the microcontroller. Table 6-1 introduces the radio transceiver I/O signals and their functionality ...
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... All bytes are transferred with MSB first. An SPI transaction is finished by releasing /SEL = H. An SPI register access consists of two bytes, a Frame Buffer or SRAM access of at least two or more bytes as described in /SEL = L enables the MISO output driver of the Atmel AT86RF232. The MSB of MISO is valid after t (see Section 12.4 1 SCLK ...
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... ADDRESS[5:0] (1) MISO PHY_STATUS Note: 1. Each SPI access can be configured to return radio controller status information (PHY_STATUS) on MISO, for details refer to Atmel AT86RF232 MOSI is sampled at the rising Bit 0 Access Mode Register access Frame Buffer access SRAM access Figure 6-4 to Figure 6-14) is set to zero after Section 6 ...
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... Register Read Access WRITE DATA XX The Atmel AT86RF232 128-byte Frame Buffer can hold the PHY service data unit (PSDU) data of one IEEE 802.15.4 compliant RX or one TX frame of maximum length at a time. A detailed description of the Frame Buffer can be found in introduction to the IEEE 802.15.4 frame format can be found in Frame Buffer read and write accesses are used to read or write frame data (PSDU and additional information) from or to the Frame Buffer ...
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... H) at any time without affecting the Frame Buffer content. Another Frame Buffer read operation starts again at the PHR field. The content of the Atmel AT86RF232 Frame Buffer is overwritten by a new received frame or a Frame Buffer write access. Figure 6-9 ...
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... For exceptions, receiving acknowledgement frames in Extended Operating Mode (TX_ARET) refer to The SRAM access mode Atmel AT86RF232 Frame Buffer or AES address space, refer to During frame receive after occurrence of interrupt IRQ_2 (RX_START) an SRAM access can be used to upload the PHR field while preserving Dynamic Frame Buffer Protection, see Section 11.6. ...
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... XX As long as /SEL = L, every subsequent byte read or byte write increments the address counter of the Frame Buffer until the SRAM access is terminated by /SEL = H. Figure 6-13 and Figure 6-14 Atmel AT86RF232 SRAM access to read and write a data package of five byte length respectively DATA 1 DATA 2 ...
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... Radio Transceiver Status information 6.3.1 Register Description 8321A–MCU Wireless–10/11 Each Atmel AT86RF232 SPI access can be configured to return status information of the radio transceiver (PHY_STATUS) to the microcontroller using the first byte of the data transferred via MISO. The content of the radio transceiver status information can be configured using register bits SPI_CMD_MODE (register 0x04, TRX_CTRL_1) ...
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... Radio Transceiver Identification 6.4.1 Register Description AT86RF232 22 The Atmel AT86RF232 can be identified by four registers. One register contains a unique part number and one register the corresponding version number. Two additional registers contain the JEDEC manufacture ID. Register 0x1C (PART_NUM): The register PART_NUM can be used for the radio transceiver identification and includes the device part number ...
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... MAN_ID_1 Description Atmel JEDEC manufacturer ID, bits[15:8] of the 32-bit JEDEC manufacturer ID are stored in register bits MAN_ID_1. Bits [7:0] are stored in register 0x1E (MAN_ID_0). The higher 16 bits of the ID are not stored in registers. AT86RF232 MAN_ID_0 MAN_ID_0 MAN_ID_1 MAN_ID_1 23 ...
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... TRX_OFF state the microcontroller forces the AT86RF232 to SLEEP by setting SLP_TR = H. If pin 17 (CLKM) provides a clock to the microcontroller this clock is switched off after 35 CLKM cycles. The AT86RF232 awakes when the microcontroller releases pin 11 (SLP_TR). The CLKM clock frequency setting for 62.5kHz are not intended to directly clock the microcontroller ...
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... IRQ_0 (PLL_LOCK) Indicates PLL lock. 8321A–MCU Wireless–10/11 The Atmel AT86RF232 differentiates between nine interrupt events (eight physical interrupt registers, one shared by two functions). Each interrupt is enabled by setting the corresponding bit in the interrupt mask register 0x0E (IRQ_MASK). Internally, each pending interrupt is stored in a separate bit of the interrupt status register. All interrupt events are OR-combined to a single external interrupt signal (IRQ pin) ...
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... Figure 6-22. IRQ_MASK_MODE = 1. IRQ_STATUS (register 0x0F) The Atmel AT86RF232 IRQ pin polarity can be configured with register bit IRQ_POLARITY (register 0x04, TRX_CTRL_1). The default behavior is active high, which means that pin 24 (IRQ issues an interrupt request. If “Frame Buffer Empty Indicator” is enabled during Frame Buffer read access the IRQ pin has an alternative functionality, refer to describes the function ...
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... All interrupts are disabled after power-on sequence (P_ON state) or reset (RESET state). Valid values are [0xFF, 0xFE, …, 0x00 IRQ_4_CCA_ED_ IRQ_5_AMI DONE IRQ_1_PLL_ IRQ_0_PLL_ UNLOCK LOCK Table 6-10 Interrupt Description in AT86RF232 IRQ_MASK IRQ_MASK IRQ_STATUS IRQ_STATUS 27 ...
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... AT86RF232 28 By reading the register after an interrupt is signaled at pin 24 (IRQ) the source of the issued interrupt can be identified. A read access to this register resets all interrupt bits, and so clears the IRQ_STATUS register. Notes register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, an interrupt event can be read from IRQ_STATUS register even if the interrupt itself is masked ...
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... A modification on IRQ_POLARITY bit has no influence to RX_BL_CTRL behavior. This setting does not affect the polarity of the “Frame Buffer Empty Indicator”, refer to Section 11.5. The Frame Buffer Empty Indicator is always active high. AT86RF232 Description Interrupt polling is disabled Masked off IRQ bits will not appear in IRQ_STATUS register ...
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... This section summarizes all states to provide the basic functionality of the Atmel AT86RF232, such as receiving and transmitting frames, the power-on sequence, and sleep. The Basic Operating Mode is designed for IEEE 802.15.4 and general ISM band applications; the corresponding radio transceiver states are shown in ...
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... P_ON – Power-On after V 8321A–MCU Wireless–10/11 If TRX_STATUS = 0x1F (STATE_TRANSITION_IN_PROGRESS) AT86RF232 is within a state transition. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS. Pin 11 (SLP_TR multifunctional pin, refer to transceiver state, a rising edge of pin 11 (SLP_TR) causes the following state transitions: ...
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... PLL_ON – PLL State AT86RF232 32 Prior to leaving P_ON, the microcontroller must set the Atmel AT86RF232 pins to the default operating values: pin 11 (SLP_TR pin 8 (/RST and pin 23 (/SEL All interrupts are disabled by default. Thus, interrupts for state transition control are to be enabled first, for example enable IRQ_4 (AWAKE_END) to indicate a state transition to TRX_OFF state or interrupt IRQ_0 (PLL_LOCK) to signal a locked PLL in PLL_ON state ...
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... The PLL_ON state corresponds to the TX_ON state in IEEE 802.15.4. In RX_ON state the receiver module and the PLL frequency synthesizer are enabled. The Atmel AT86RF232 receive mode is internally separated into RX_ON state and BUSY_RX state. There is no difference between these states with respect to the analog radio transceiver circuitry, which is always turned on ...
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... IRQ_3 (TRX_END) interrupt and returns into PLL_ON state. The RESET state is to reset all registers and state machines of the AT86RF232 to their default values, exception are register bits CLKM_CTRL (register 0x03, TRX_CTRL_0). These register bits require a specific treatment, for details see A reset forces the radio transceiver into TRX_OFF state ...
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... Frame Content TRX_STATE IRQ Interrupt latency 8321A–MCU Wireless–10/11 All interrupts provided by the Atmel AT86RF232 (see Basic Operating Mode. For example, interrupts are provided to observe the status of radio transceiver RX and TX operations. On reception IRQ_2 (RX_START) indicates the detection of a valid PHR first, IRQ_5 (AMI) an address match and IRQ_3 (TRX_END) the completion of the frame reception ...
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... Basic Operating Mode Timing 7.1.4.1 Power-on Procedure 7.1.4.2 Wake-up Procedure AT86RF232 36 The following paragraphs depict Atmel AT86RF232 state transitions and their timing properties. Timing figures are explained in The power-on procedure to P_ON state is shown in Figure 7-3. Power-on Procedure to P_ON State. 0 100 Event State P_ON ...
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... Starting from PLL_ON state it is further assumed that the PLL is already locked. A transmission is initiated either by a rising edge of pin 11 (SLP_TR command TX_START, the Atmel AT86RF232 changes into BUSY_TX state. The PLL settles to the transmit frequency and the PA is enabled. t initiating the transmission starts the internally generated SHR transmission. After that the PSDU data are transmitted from the Frame Buffer ...
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... If the radio transceiver was in state SLEEP, the XOSC and DVREG are enabled before entering TRX_OFF state. If register bits TRX_STATUS indicates STATE_TRANSITION_IN_PROGRESS during system initialization until the Atmel AT86RF232 reaches TRX_OFF state, do not try to initiate a further state change while the radio transceiver is in this state. Notes: 2 ...
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... TR13 t Various statesPLL_ON TR14 t P_ONTRX_OFF TR15 8321A–MCU Wireless–10/11 The Atmel AT86RF232 transition numbers correspond to SPI access time unless otherwise stated. See measurement setup in Condition Depends on crystal oscillator setup (C = 10pF) and external L capacitor at DVDD (100nF nom.). Depends on crystal oscillator ...
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... Table 7-2. Atmel AT86RF232 Block Initialization and Settling Time. Symbol Parameter t Reference oscillator settling time XTAL t FTN calibration time FTN t DVREG settling time DVREG t AVREG settling time AVREG t Initial PLL settling time PLL_INIT t PLL settling time on channel switch PLL_SW t PLL CF calibration PLL_CF ...
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... STATE_TRANSITION_IN_PROGRESS. State transition timings are defined in Table 7- reserved TRX_STATUS TRX_STATUS Description P_ON BUSY_RX BUSY_TX RX_ON TRX_OFF (CLK Mode) PLL_ON (TX_ON) SLEEP BUSY_RX_AACK BUSY_TX_ARET RX_AACK_ON TX_ARET_ON STATE_TRANSITION_IN_PROGRESS All other values are reserved AT86RF232 TRX_STATUS TRX_STATUS Section 7.2. 41 ...
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... AT86RF232 42 Register 0x02 (TRX_STATE): The radio transceiver states are controlled via register TRX_STATE using register bits TRX_CMD. The read-only register bits TRAC_STATUS indicate the status or result of an Extended Operating Mode transaction. Figure 7-9. Register TRX_STATE. Bit 7 0x02 TRAC_STATUS Read/Write R Reset value 0 Bit ...
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... Dependent on the value of the frame pending subfield in the received acknowledgement frame the transaction status is set, see TRAC_STATUS, Section An Atmel AT86RF232 state diagram including the Extended Operating Mode states is shown in Figure 7-10. Yellow marked states represent the Basic Operating Mode; blue marked states represent the Extended Operating Mode ...
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... Figure 7-10. Extended Operating Mode State Diagram. P_ON (Power-on after V XOSC=ON Pull=ON FORCE_TRX_OFF (all states except SLEEP) SHR Detected BUSY_RX (Receive State) Frame End From / To TRX_OFF SHR Detected BUSY_RX_AACK Trans- action Finished AT86RF232 44 SLEEP ) (Sleep State) DD XOSC=OFF Pull=OFF TRX_OFF 12 (Clock State) XOSC=ON Pull=OFF RX_ON ...
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... The TX_ARET transaction is started with a rising edge of pin 11 (SLP_TR) or writing the command TX_START to register bits TRX_CMD. The TX_ARET state is left by writing a new command to the register bits TRX_CMD. If the AT86RF232 is within a CSMA-CA transaction, a frame transmission or an acknowledgment procedure (BUSY_TX_ARET), the state change is executed after finishing. Alternatively, the command FORCE_TRX_OFF or FORCE_PLL_ON can be used to instantly terminate the TX_ARET transaction and change into radio transceiver state TRX_OFF or PLL_ON, respectively ...
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... CSMA-CA retries after a busy channel is detected. The register bits CSMA_SEED (registers 0x2D, 0x2E) define a random seed for the back-off-time random-number generator in the Atmel AT86RF232. The register bits MAX_BE and MIN_BE (register 0x2F, CSMA_BE) set the maximum and minimum CSMA back-off exponent (see [1]), respectively. ...
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... IRQ_3 (TRX_END) interrupt is issued, even if the FCS fails. During reception the Atmel AT86RF232 parses bit[5] (ACK Request) of the frame control field of the received data or MAC command frame to check if an ACK reply is expected. In that case and if the frame passes the third level of filtering, see IEEE 802 ...
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... Promiscuous Mode and Reserved Frame Types Note 2: FCS check is omitted for Promiscous Mode Note 3: Additional conditions: - ACK requested & - AACK_DIS_ACK==0 & - frame_version<=AACK_FVN_MODE Wait 2 symbol periods pin 11 (SLP_TR) rising edge Y AT86RF232 48 TRX_STATE = RX_AACK_ON N SHR detected Y TRX_STATE = BUSY_RX_AACK Generate IRQ_2 (RX_START) Scanning MHR N Frame Filtering ...
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... The usage of the RX_AACK configuration bits for various operating modes of a node is explained in the following sections. Configuration bits not mentioned in the following two sections should be set to their reset values according to All registers mentioned in Table 7-5 The general behavior of the “Atmel AT86RF232 Extended Feature Set”, settings: o ANT_DIV (Antenna Diversity) o RX_PDT_LEVEL (blocking frame reception of lower power signals) are completely independent from RX_AACK mode and can be arbitrarily combined ...
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... Configuration of IEEE Scenarios AT86RF232 50 Normal Device Table 7-6 shows a typical Atmel AT86RF232 RX_AACK configuration of an IEEE 802.15.4 device operating as a normal device, rather than a PAN coordinator or router. Table 7-6. Configuration of IEEE 802.15.4 Devices. Register Register Register Name Address Bits 0x20,0x21 SHORT_ADDR_0/1 0x22,0x23 PAN_ADDR_0/1 ...
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... Wireless–10/11 PAN-Coordinator Table 7-7 shows the Atmel AT86RF232 RX_AACK configuration for a PAN coordinator. Table 7-7. Configuration of a PAN Coordinator. Register Register Register Name Address Bits 0x20,0x21 SHORT_ADDR_0/1 0x22,0x23 PAN_ADDR_0/1 0x24 IEEE_ADDR_0 … … 0x2B IEEE_ADDR_7 0x0C 7 RX_SAFE_MODE 0x2C 0 SLOTTED_OPERATION 0x2E ...
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... AACK_FVN_MODE If the Atmel AT86RF232 radio transceiver is in promiscuous mode, second level of filtering according to IEEE 802.15.4-2006, Section 7.5.6.2, is applied to a received frame. However, an IRQ_3 (TRX_END) is issued even if the FCS is invalid. Thus necessary to read register bit RX_CRC_VALID (register 0x06, PHY_RSSI) after IRQ_3 (TRX_END) in order to verify the reception of a frame with a valid FCS ...
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... Configuration of non IEEE 802.15.4 Compliant Scenarios 8321A–MCU Wireless–10/11 Sniffer Table 7-9 shows an Atmel AT86RF232 RX_AACK configuration to setup a sniffer device. Other RX_AACK configuration bits, refer to reset values. All frames received are indicated by an IRQ_2 (RX_START) and IRQ_3 (TRX_END). After frame reception register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is updated with the result of the FCS check (see needs to be checked in order to dismiss corrupted frames ...
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... AT86RF232 54 Register Register Register Name Address Bits 0x2E 3 AACK_I_AM_COORD 0x2E 4 AACK_DIS_ACK 0x2E 7:6 AACK_FVN_MODE There are three different options for handling reserved frame types. 1. AACK_UPLD_RES_FT = 1, AACK_FLT_RES_FT = 0: Any non-corrupted frame with a reserved frame type is indicated by an IRQ_3 (TRX_END) interrupt. No further address filtering is applied on those frames. ...
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... To accept a received frame and to generate an address match interrupt IRQ_5 (AMI) a filtering procedure as described in IEEE 802.15.4-2006 Section 7.5.6.2. (Third level of filtering) is applied to the frame. The Atmel AT86RF232 RX_AACK mode accepts only frames that satisfy all of the following requirements (quote from IEEE 802.15.4-2006, Section 7.5.6.2): 1 ...
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... Filter rule one is affected by register bits AACK_FLTR_RES_FT and AACK_UPLD_RES_FT, 2. Filter rule two is affected by register bits AACK_FVN_MODE, Atmel AT86RF232 supports IEEE 802.15.4-2006, Section 7.5.6.4.2, in conjunction with the microcontroller. In RX_AACK mode with register bit SLOTTED_OPERATION (register 0x2C, XAH_CTRL_0) set, the transmission of an acknowledgement frame has to be controlled by the microcontroller ...
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... RX_AACK_ON RX/TX IRQ Typ. Processing Delay 8321A–MCU Wireless–10/11 A timing example of an RX_AACK transaction is shown in a data frame of length 10 with an ACK request is received. The Atmel AT86RF232 changes to state BUSY_RX_AACK after SFD detection. The completion of the frame reception is indicated by IRQ_2 (RX_START) and IRQ_5 (AMI) are disabled in this example. The ACK frame is automatically transmitted after a default wait period of 12 symbols (192µ ...
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... TX_ARET_ON – Transmit with Automatic Frame Retransmission and CSMA-CA Retry AT86RF232 58 Figure 7-14. Flow Diagram of TX_ARET. TRX_STATE = TX_ARET_ON frame_rctr = 0 N Start TX Y TRX_STATE = BUSY_TX_ARET TRAC_STATUS = INVALID (see Note 1) N MAX_CSMA_RETRIES <7 Y csma_rctr = 0 Random Back-Off csma_rctr = csma_rctr + 1 CCA Failure CCA Result Success Transmit Frame ...
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... Wireless–10/11 Overview The implemented TX_ARET algorithm is shown in In TX_ARET mode, the Atmel AT86RF232 first executes the CSMA-CA algorithm, as defined by IEEE 802.15.4–2006, Section 7.5.1.4, initiated by a transmit start event. If the channel is IDLE a frame is transmitted from the Frame Buffer. If the acknowledgement frame is requested the radio transceiver additionally checks for an ACK reply ...
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... TR10 Here an example data frame of length 10 with an ACK request is transmitted. After that the Atmel AT86RF232 switches to receive mode and expects an acknowledgement response. During the whole transaction including frame transmit, wait for ACK and ACK receive the radio transceiver status register bits TRX_STATUS (register 0x01, TRX_STATUS) signals BUSY_TX_ARET ...
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... TRX_STATE) change to either TRAC_STATUS = SUCCESS, or TRAC_STATUS = SUCCESS_DATA_PENDING if the frame pending subfield of the received ACK frame was set to one. The Atmel AT86RF232 interrupt handling in the Extended Operating Mode is similar to the Basic Operating Mode, refer to by setting the appropriate bit in register 0x0E (IRQ_MASK). ...
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... Register Summary 7.2.7 Register Description – Control Registers AT86RF232 62 The following Atmel AT86RF232 registers are to be configured to control the Extended Operating Mode: Table 7-14. Register Summary. Reg.-Addr. Register Name 0x01 TRX_STATUS 0x02 TRX_STATE 0x04 TRX_CTRL_1 0x08 PHY_CC_CCA 0x09 CCA_THRES 0x17 XAH_CTRL_1 0x19 XAH_CTRL_2 0x20 – ...
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... Extended Operating Mode transaction. Figure 7-17. Register TRX_STATE. Bit 7 0x02 TRAC_STATUS Read/Write R Reset value 0 Bit 3 0x02 Read/Write R/W R/W Reset value 0 Description PLL_ON (TX_ON) SLEEP BUSY_RX_AACK BUSY_TX_ARET RX_AACK_ON TX_ARET_ON STATE_TRANSITION_IN_PROGRESS All other values are reserved TRX_CMD TRX_CMD R/W R AT86RF232 TRX_STATE TRX_STATE 63 ...
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... AT86RF232 64 Bit 7:5 – TRAC_STATUS Table 7-16. TRAC_STATUS. Register Bits Value Description (1) TRAC_STATUS 0 SUCCESS 1 SUCCESS_DATA_PENDING 2 SUCCESS_WAIT_FOR_ACK 3 CHANNEL_ACCESS_FAILURE 5 NO_ACK (1) 7 INVALID All other values are reserved Note: 1. Even though the reset value for register bits TRAC_STATUS is zero, the RX_AACK and TX_ARET procedures set the register bits to TRAC_STATUS = 7 (INVALID) when they are started ...
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... IRQ_2_EXT_EN Read/Write R/W R/W Reset value 0 Bit 3 0x04 SPI_CMD_MODE Read/Write R/W R/W Reset value 0 Description NOP TX_START FORCE_TRX_OFF FORCE_PLL_ON RX_ON TRX_OFF (CLK Mode) PLL_ON (TX_ON) RX_AACK_ON TX_ARET_ON All other values are reserved TX_AUTO_CRC_ RX_BL_CTRL ON R/W R IRQ_MASK_MODE IRQ_POLARITY R/W R AT86RF232 TRX_CTRL_1 TRX_CTRL_1 65 ...
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... AT86RF232 66 Bit 5 - TX_AUTO_CRC_ON The register bit TX_AUTO_CRC_ON controls the automatic FCS generation for transmit operations. Table 7-18. TX_AUTO_CRC_ON. Register Bits Value TX_AUTO_CRC_ON 0 1 Note: 1. The TX_AUTO_CRC_ON function can be used within Basic and Extended Operating Modes. For further details refer to Section Register 0x17 (XAH_CTRL_1): The XAH_CTRL_1 register is a multi-purpose control register for Extended Operating Mode ...
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... MAC command frame. This is achieved with the reset value of the register bit AACK_ACK_TIME. Alternatively, if AACK_ACK_TIME = 1 an acknowledgment frame is sent already two symbol periods after the reception of the last symbol of a data or MAC command frame. AT86RF232 Description Filtering reserved frame types is disabled Filtering reserved frame types is enabled ...
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... AT86RF232 68 Bit 1 - AACK_PROM_MODE The register bit AACK_PROM_MODE enables the promiscuous mode, within the RX_AACK mode. Table 7-23. AACK_PROM_MODE. Register Bits Value AACK_PROM_MODE 0 1 Refer to IEEE 802.15.4-2006, Section 7.5.6.5. If this register bit is set, every incoming frame with a valid PHR finishes with IRQ_3 (TRX_END) interrupt even if the third level filter rules do not match or the FCS is not valid ...
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... MAX_FRAME_RETRIES R/W R SLOTTED_ OPERATION R/W R Description The setting of MAX_FRAME_RETRIES in TX_ARET mode specifies the number of attempts to retransmit a frame, when it was not acknowledged by the recipient, before the transaction gets cancelled. Valid values are [0x7, 0x6, …, 0x0]. AT86RF232 XAH_CTRL_0 XAH_CTRL_0 69 ...
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... AT86RF232 70 Bit 3:1 - MAX_CSMA_RETRIES Number of retries in TX_ARET mode to repeat the CSMA-CA procedure before the transaction gets cancelled. Table 7-27. MAX_CSMA_RETRIES. Register Bits Value (1) MAX_CSMA_RETRIES 0 (1) 1 (1) 2 (1) 3 (1) 4 (1) 5 (3) 7 Notes: 1. MAX_CSMA_RETRIES specifies the number of retries in TX_ARET mode to repeat the CSMA-CA procedure before the transaction gets cancelled. According to IEEE 802.15.4 the valid range of MAX_CSMA_RETRIES is [5, 4, … ...
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... The higher 3-bit are part of register bits CSMA_SEED_1 (register 0x2E, CSMA_SEED_1). CSMA_SEED is the seed for the random number generation that determines the length of the back-off period in the CSMA-CA algorithm AACK_SET_PD AACK_DIS_ACK R/W R CSMA_SEED_1 R/W R AT86RF232 CSMA_SEED_0 CSMA_SEED_0 CSMA_SEED_1 CSMA_SEED_1 71 ...
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... The frame control field of the MAC header (MHR) contains a frame version subfield. The setting of register bits AACK_FVN_MODE specifies the frame filtering behavior of the Atmel AT86RF232. According to the content of these register bits the radio transceiver passes frames with a specific frame version number, number group, or independent of the frame version number ...
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... PAN coordinator addressing is disabled PAN coordinator addressing is enabled Description These register bits are the higher 3-bit of the CSMA_SEED, bits [10:8]. The lower part is in register 0x2D (CSMA_SEED_0), see register CSMA_SEED_0 for details MAX_BE R/W R MIN_BE R/W R AT86RF232 CSMA_BE CSMA_BE 73 ...
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... AT86RF232 74 Bit 7:4 - MAX_BE Maximum back-off exponent in the CSMA-CA algorithm. Table 7-35. MAX_BE. Register Bits Value MAX_BE 0x5 For details refer to IEEE 802.15.4-2006, Section 7.5.1.4. Bit 3:0 - MIN_BE Minimum back-off exponent in the CSMA-CA algorithm. Table 7-36. MIN_BE. Register Bits Value MIN_BE 0x3 For details refer to IEEE 802.15.4-2006, Section 7.5.1.4. ...
Page 75
... Bit 7 0x22 Read/Write R/W R/W Reset value 1 Bit 3 0x22 Read/Write R/W R/W Reset value SHORT_ADDR_0 R/W R SHORT_ADDR_0 R/W R SHORT_ADDR_1 R/W R SHORT_ADDR_1 R/W R PAN_ID_0 R/W R PAN_ID_0 R/W R AT86RF232 SHORT_ADDR_0 SHORT_ADDR_0 SHORT_ADDR_1 SHORT_ADDR_1 PAN_ID_0 PAN_ID_0 75 ...
Page 76
... AT86RF232 76 Register 0x23 (PAN_ID_1): This register contains the higher 8-bit of the MAC PAN ID for Frame Filter address recognition, bits[15:8]. Figure 7-28. Register PAN_ID_1. Bit 7 0x23 Read/Write R/W R/W Reset value 1 Bit 3 0x23 Read/Write R/W R/W Reset value 1 Register 0x24 (IEEE_ADDR_0): This register contains the lower 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[7:0] ...
Page 77
... Bit 7 0x28 Read/Write R/W R/W Reset value 0 Bit 3 0x28 Read/Write R/W R/W Reset value IEEE_ADDR_2 R/W R IEEE_ADDR_2 R/W R IEEE_ADDR_3 R/W R IEEE_ADDR_3 R/W R IEEE_ADDR_4 R/W R IEEE_ADDR_4 R/W R AT86RF232 IEEE_ADDR_2 IEEE_ADDR_2 IEEE_ADDR_3 IEEE_ADDR_3 IEEE_ADDR_4 IEEE_ADDR_4 77 ...
Page 78
... AT86RF232 78 Register 0x29 (IEEE_ADDR_5): This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[47:40]. Figure 7-34. Register IEEE_ADDR_5. Bit 7 0x29 Read/Write R/W R/W Reset value 0 Bit 3 0x29 Read/Write R/W R/W Reset value 0 Register 0x2A (IEEE_ADDR_6): This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[55:48] ...
Page 79
... On reception, the PHR is returned as the first octet during Frame Buffer read access. While the IEEE 802.15.4-2006 standard declares bit seven of the PHR octet as being reserved, the AT86RF232 preserves this bit upon transmission and reception so it can be used to carry additional information within proprietary networks. Nevertheless, this bit is not considered to be part of the frame length, so only frames between one and 127 octets are possible ...
Page 80
... Frame Frame Type Enabled Pending 8.1.2.1 MAC Header (MHR) Fields 8.1.2.2 Frame Control Field (FCF) AT86RF232 80 The PSDU has a variable length between zero and aMaxPHYPacketSize (127, maximum PSDU size in octets). The length of the PSDU is signaled by the frame length field (PHR), refer to Table 8-1. The PSDU contains the MAC Protocol Layer Data Unit (MPDU) ...
Page 81
... This subfield is used for address filtering by the third level filter rules. By default, only frame types 0 – 3 pass the third level filter rules, refer to address filtering by the Atmel AT86RF232 is enabled when using the RX_AACK mode, refer to Section 7.2.3. However, a reserved frame (frame type value > 3) can be received if register bit ...
Page 82
... In RX_AACK mode, this bit is evaluated by the address filter logic of the Atmel AT86RF232. This subfield was previously named “Intra-PAN”. Bit [11:10]: the “Destination Addressing Mode” subfield describes the format of the destination address of the frame. The values of the address modes are summarized in Table 8-3, according to IEEE 802 ...
Page 83
... The addressing fields of the MPDU are used by the Atmel AT86RF232 for address matching indication. The destination address (if present) is always first, followed by the source address (if present). Each address field consists of the PAN-ID and a device address. If both addresses are present, and the “ ...
Page 84
... The Atmel AT86RF232 applies an FCS check on each received frame. The FCS check result is stored in register bit RX_CRC_VALID (register 0x06, PHY_RSSI). On transmission the radio transceiver generates and appends the FCS bytes during the frame transmission ...
Page 85
... The automatic FCS generation is activated with register bit TX_AUTO_CRC_ON = 1 (reset value). This allows the Atmel AT86RF232 to compute the FCS autonomously. For a frame with a frame length specified ≤ N ≤ 127), the FCS is calculated on the first N-2 octets in the Frame Buffer, and the resulting FCS field is transmitted in place of the last two octets from the Frame Buffer. If the radio transceiver’ ...
Page 86
... Register Description AT86RF232 86 Register 0x04 (TRX_CTRL_1): The TRX_CTRL_1 register is a multi-purpose register to control various operating modes and settings of the radio transceiver. Figure 8-4. Register TRX_CTRL_1. Bit 7 0x04 reserved IRQ_2_EXT_EN Read/Write R/W R/W Reset value 0 Bit 3 0x04 SPI_CMD_MODE Read/Write R/W R/W Reset value 0 Bit 5 - TX_AUTO_CRC_ON The register bit TX_AUTO_CRC_ON controls the automatic FCS generation for transmit operations ...
Page 87
... Reading this register bit indicates whether the last received frame has a valid FCS or not. The register bit is updated when issuing interrupt IRQ_3 (TRX_END) and remains valid until the next TRX_END interrupt is issued, caused by a new frame reception. AT86RF232 Description FCS is not valid ...
Page 88
... Overview 8.3.2 Reading RSSI 8.3.3 Data Interpretation AT86RF232 88 The Atmel AT86RF232 Received Signal Strength Indicator is characterized by: Minimum RSSI level is -91dBm (RSSI Dynamic range is 87dB Minimum RSSI value is 0 Maximum RSSI value is 28 The RSSI is a 5-bit value indicating the receive power in the selected channel, in steps of 3dB ...
Page 89
... RF input power power of P ≥ -7dBm (see parameter RSSI RND_VALUE RSSI RSSI Description Minimum RSSI value Maximum RSSI value ≤ -91dBm (RSSI RF specified in Section MAX AT86RF232 PHY_RSSI PHY_RSSI ), a value of 28 BASE_VAL 12.7). 89 ...
Page 90
... Energy Detection (ED) 8.4.1 Overview 8.4.2 Measurement Description AT86RF232 90 The Atmel AT86RF232 Energy Detection (ED) module is characterized by: 84 unique energy levels defined 1dB resolution The receiver ED measurement is used by the network layer as part of a channel selection algorithm estimation of the received signal power within the bandwidth of an IEEE 802 ...
Page 91
... PHY_ED_LEVEL is an Atmel AT86RF232 has a valid range from 0x00 to 0x53 with a resolution of 1dB. A value of 0xFF indicates the reset value. All other values do not occur. Due to environmental conditions (temperature, voltage, semiconductor parameters, etc.) the calculated ED_LEVEL value has a maximum tolerance of ±5dB, this considered as constant offset over the measurement range ...
Page 92
... Register Description AT86RF232 92 Register 0x07 (PHY_ED_LEVEL): The PHY_ED_LEVEL register contains the result measurement. Figure 8-9. Register PHY_ED_LEVEL. Bit 7 0x07 Read/Write R Reset value 1 Bit 3 0x07 Read/Write R Reset value 1 Bit 7:0 - ED_LEVEL The register bits ED_LEVEL signals the ED level for current channel. Table 8-9. ED_LEVEL. ...
Page 93
... The CCA modes are configurable via register 0x08 (PHY_CC_CCA). Using the Basic Operating Mode, a CCA request can be initiated manually by setting CCA_REQUEST = 1 (register 0x08, PHY_CC_CCA), if the Atmel AT86RF232 is in any RX state. The current channel status (CCA_STATUS) and the CCA completion status (CCA_DONE) are accessible in register 0x01 (TRX_STATUS). ...
Page 94
... Interrupt Handling 8.5.5 Measurement Time AT86RF232 94 The Atmel AT86RF232 current channel status (CCA_STATUS) and the CCA completion status (CCA_DONE) are accessible in register 0x01 (TRX_STATUS). Note, register bits CCA_DONE and CCA_STATUS are cleared in response to a CCA_REQUEST. The completion of a measurement cycle is indicated by CCA_DONE = 1. If the radio transceiver detected no signal (idle channel) during the measurement cycle, the CCA_STATUS bit is set to one ...
Page 95
... IRQ_4 (CCA_ED_DONE). The variation of a CCA measurement period in BUSY_RX state is described recommended to perform CCA measurements in Atmel AT86RF232 RX_ON state only. To avoid switching accidentally to BUSY_RX state the SHR detection can be disabled by setting register bit RX_PDT_DIS (register 0x15, RX_SYN), refer to Section 9 ...
Page 96
... AT86RF232 96 Bit 7 - CCA_DONE Table 8-12. CCA_DONE. Register Bits Value CCA_DONE 0 1 The register bit CCA_DONE indicates if a CCA request is completed. This is also indicated by an interrupt IRQ_4 (CCA_ED_DONE). The register bit CCA_DONE is cleared in response to a CCA_REQUEST. Bit 6 - CCA_STATUS Table 8-13. CCA_STATUS. Register Bits ...
Page 97
... Mode 3b, Carrier sense AND energy above threshold reserved R/W R CCA_ED_THRES R/W R Description The CCA Mode 1 request indicates a busy channel if the measured received power is above RSSI_BASE_VAL + 2 x CCA_ED_THRES [dB]. CCA Modes 0 and 3 are logical related to this result. AT86RF232 CCA_THRES CCA_THRES 97 ...
Page 98
... LQI values in between should be uniformly distributed between these two limits. The LQI measurement of the Atmel AT86RF232 is implemented as a measure of the link quality which can be described with the packet error rate (PER) for this link. An LQI value can be associated with an expected packet error rate ...
Page 99
... Note: 1. The received signal power as indicated by received signal strength indication (RSSI) value or energy detection (ED) value of the Atmel AT86RF232 do not characterize the signal quality and the ability to decode a signal example, a received signal with an input power of about 6dB above the receiver sensitivity likely results in a LQI value close to 255 for radio channels with very low signal distortions ...
Page 100
... Module Description 9.1 Receiver (RX) 9.1.1 Overview 9.1.2 Frame Receive Procedure 9.1.3 Configuration AT86RF232 100 The Atmel AT86RF232 receiver is split into an analog radio front-end and a digital base band processor (RX BBP), see Figure Figure 9-1. Receiver Block Diagram. LO RFP LNA PPF RFN The differential RF signal is amplified by a low noise amplifier (LNA), filtered (PPF) and down converted to an intermediate frequency by a mixer ...
Page 101
... TRX_OFF or PLL_ON by writing the command RX_AACK_ON. There is no additional configuration required to receive IEEE 802.15.4 compliant frames when using the Basic Operating Mode. However, the frame reception in the Atmel AT86RF232 Extended Operating Mode requires further register configurations, for details refer to Section 7 ...
Page 102
... AT86RF232 102 Bit 3:0 - RX_PDT_LEVEL The register bits RX_PDT_LEVEL desensitize the receiver in steps of 3dB. Table 9-2. RX_PDT_LEVEL. Register Bits Value RX_PDT_LEVEL 0x00 0x0F These register bits desensitize the receiver such that frames with an RSSI level below the RX_PDT_LEVEL threshold level (if RX_PDT_LEVEL > 0) are not received. For a RX_PDT_LEVEL > ...
Page 103
... TRX_STATE PLL_ON SLP_TR PA buffer PA Modulation 8321A–MCU Wireless–10/11 The Atmel AT86RF232 transmitter consists of a digital base band processor (TX BBP) and an analog radio front end, see Figure 9-3. Transmitter Block Diagram. Ext. RF front-end and Output Power Control RFP PA Buf PLL – TX Modulation ...
Page 104
... TX Power Ramping 9.2.5 Register Description AT86RF232 104 To optimize the output power spectral density (PSD), the PA buffer and PA are enabled sequentially, see in Figure 9-4. In this example the transmission is initiated with the rising edge of pin 11 (SLP_TR). The radio transceiver state changes from PLL_ON to BUSY_TX. The modulation of the frame starts 16µs after SLP_TR rising edge. ...
Page 105
... Frame Buffer 9.3.1 Data Management 8321A–MCU Wireless–10/11 The Atmel AT86RF232 contains a 128 byte dual port SRAM. One port is connected to the SPI interface, the other to the internal transmitter and receiver modules. For data communication, both ports are independent and simultaneously accessible. ...
Page 106
... A radio transceiver state change, except a transition to SLEEP, or RESET state, does not affect the Frame Buffer contents. If the radio transceiver is forced into SLEEP, the Frame Buffer is powered off and the stored data gets lost. The Atmel AT86RF232 supports an IEEE 802.15.4 compliant frame format as shown in Figure 9-6. ...
Page 107
... Wireless–10/11 While receiving a frame, primarily the data needs to be stored in the Atmel AT86RF232 Frame Buffer before reading it. This can be ensured by accessing the Frame Buffer 32µs after IRQ_2 (RX_START) at the earliest. When reading the frame data continuously the SPI data rate shall be lower than 250kb/s to ensure no under run interrupt occurs ...
Page 108
... Low dropout (LDO) voltage regulator Configurable for usage of external voltage regulator The internal voltage regulators supply a stabilized voltage to the Atmel AT86RF232. The AVREG provides the regulated 1.8V supply voltage for the analog section and the DVREG supplies the 1.8V supply voltage for the digital section. ...
Page 109
... Description Analog voltage regulator is disabled or supply voltage not stable Analog supply voltage has been settled Description Internal voltage regulator enabled, digital section Internal voltage regulator disabled, use external regulated 1.8V supply voltage for the digital section AT86RF232 VREG_CTRL VREG_CTRL 109 ...
Page 110
... AT86RF232 110 Bit 2 - DVDD_OK This register bit indicates if the internal 1.8V regulated voltage supply DVDD has settled. The bit is set to logic high, if DVREG_EXT = 1. Table 9-8. DVDD_OK. Register Bits Value DVDD_OK 0 1 Note: 1. While the reset value of this bit is zero, any practical access to the register is only possible when DVREG is active ...
Page 111
... Configurable voltage threshold range: 1.7V to 3.675V Generates an interrupt when supply voltage drops below a threshold The Atmel AT86RF232 battery monitor (BATMON) detects and indicates a low supply voltage of the external supply voltage at pin 28 (EVDD). This is done by comparing the voltage on the external supply pin 28 (EVDD) with a configurable internal threshold voltage ...
Page 112
... A supply voltage drop below the configured threshold value is indicated by an interrupt IRQ_7 (BAT_LOW), see Section Note: 1. The Atmel AT86RF232 IRQ_7 (BAT_LOW) interrupt is issued only if BATMON_OK changes from one to zero. No interrupt is generated when: The battery voltage is under the default 1.8V threshold at power-on (BATMON_OK was never one), or ...
Page 113
... AT86RF232 Description Enables the low range, see BATMON_VTH Enables the high range, see BATMON_VTH Voltage [V] BATMON_HR = 1 BATMON_HR = 0 2.550 2.625 2.700 2.775 2.850 2.925 3.000 3.075 3.150 3 ...
Page 114
... Configurable trimming capacitance array Configurable clock output (CLKM) The crystal oscillator generates the reference frequency for the Atmel AT86RF232. All other internally generated frequencies of the radio transceiver are derived from this unique frequency. Therefore, the overall system performance is mainly determined by the accuracy of crystal reference frequency ...
Page 115
... C L TRIM The Atmel AT86RF232 trimming capacitors provide the possibility of reducing frequency deviations caused by production process variations or by external components tolerances. Note that the oscillation frequency can only be reduced by increasing the trimming capacitance. The frequency deviation caused by one step of C decreases with increasing crystal load capacitor values ...
Page 116
... CLKM clock rate change. Otherwise (CLKM_SHA_SEL = 1) the new clock rate is supplied when leaving the SLEEP state the next time. To reduce power consumption and spurious emissions recommended to turn off the Atmel AT86RF232 CLKM clock when not in use. Note: 1. During reset procedure, see are shadowed ...
Page 117
... Internal crystal oscillator disabled, use external reference frequency Internal crystal oscillator enabled and XOSC voltage regulator enabled All other values are reserved Description A capacitance value in the range from 0pF to 4.5pF is selectable with a resolution of 0.3pF. Valid values are [0xF, 0xE, …, 0x0]. AT86RF232 XOSC_CTRL XOSC_CTRL 117 ...
Page 118
... Two PLL-interrupts for status indication Fast PLL settling to support frequency hopping The PLL generates the RF frequencies for the Atmel AT86RF232. During receive operation the frequency synthesizer works as a local oscillator on the radio transceiver receive frequency, during transmit operation the voltage-controlled oscillator (VCO) is directly modulated to generate the RF transmit signal ...
Page 119
... Interrupt Handling 9.7.6 Register Description 8321A–MCU Wireless–10/11 If the Atmel AT86RF232 PLL operates for a long time on the same channel, for example more than five minutes, or the operating temperature changes significantly recommended to initiate the calibration loops manually. Both calibration loops can be initiated manually by setting PLL_CF_START = 1 (register 0x1A, PLL_CF) and register bit PLL_DCU_START = 1 (register 0x1B, PLL_DCU) ...
Page 120
... AT86RF232 120 Bit 4:0 – CHANNEL The register bits CHANNEL define the RX/TX channel. The channel assignment is according to IEEE 802.15.4. Table 9-16. Channel Assignment for IEEE 802.15.4 – 2.4GHz Band. Register Bits Value CHANNEL 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 ...
Page 121
... Center frequency calibration cycle is finished Initiates center frequency calibration cycle Description Initial CF start word Valid values are [0xF, 0xE, …, 0x0 reserved R R/W R reserved R/W R Description Delay cell calibration cycle is finished Initiates delay cell calibration cycle AT86RF232 PLL_DCU PLL_DCU 121 ...
Page 122
... Register Description AT86RF232 122 The Atmel AT86RF232 FTN is incorporated to compensate device tolerances for temperature, supply voltage variations as well as part-to-part variations of the radio transceiver. The filter-tuning result is used to correct the analog baseband filter transfer function and the PLL loop-filter time constant, refer to An FTN calibration cycle is initiated automatically when entering the TRX_OFF state from the P_ON, SLEEP, or RESET state ...
Page 123
... Wireless–10/11 This section describes basic procedures to receive and transmit frames using the Atmel AT86RF232. For a detailed programming description refer to reference [6]. A frame reception comprises of two actions: The PHY listens for, receives and demodulates the frame to the Frame Buffer and signalizes the reception to the microcontroller ...
Page 124
... TRX_CMD (register 0x02, TRX_STATE), while the radio transceiver is in state PLL_ON or TX_ARET_ON. The completion of the transaction is indicated by interrupt IRQ_3 (TRX_END). Figure 10-2. Transaction between AT86RF232 and Microcontroller during Transmit. Write frame data (Frame Buffer access) Write TRX_CMD = TX_START, or assert pin 11 (SLP_TR) ...
Page 125
... The security module is based on an AES-128 core according to FIPS197 standard, refer to [5]. The security module works independent of other building blocks of the Atmel AT86RF232, encryption and decryption can be performed in parallel to a frame transmission or reception. Controlling the security block is implemented as an SRAM access to address space 0x82 to 0x94 ...
Page 126
... AES_KEY. Note: 1. ECB decryption is not required for IEEE 802.15.4 or ZigBee security processing. The Atmel AT86RF232 provides this functionality as an additional feature. ECB is the basic operating mode of the security module. After setting up the initial AES key, register bits AES_MODE = 0 (SRAM address 0x83, AES_CTRL) sets up ECB mode ...
Page 127
... ECB, encryption Summarizing, the following steps are required to perform a security operation using only one Atmel AT86RF232 SPI access: 1. Configure SPI access 2. Configure AES operation 3. Write 128-bit data block 4. Start AES operation This sequence is recommended because the security operation is configured and started within one SPI transaction ...
Page 128
... After preparing the AES key and defining the AES operation direction using Atmel AT86RF232 SRAM register bit AES_DIR, the data has to be provided to the AES engine and the CBC operation can be started. The first CBC run has to be configured as ECB to process the initial data (plaintext XORed with an initialization vector provided by the microcontroller) ...
Page 129
... AES processing of the data is usually faster than the transfer of the data via the SPI interface. To reduce the overall processing time the Atmel AT86RF232 provides a Fast SRAM access for the address space 0x82 to 0x94. AES run #0 AES access #1 P15 ...
Page 130
... AES SRAM Configuration Register AT86RF232 130 The Fast SRAM access automatically applies to all write operations to SRAM addresses 0x82 to 0x94. A security operation is started within one Atmel AT86RF232 SRAM access by appending the start AES_CTRL_MIRROR) to the SPI sequence. Register AES_CTRL_MIRROR is a mirrored version of register 0x83 (AES_CTRL). ...
Page 131
... No error of the AES module AES module error Description AES module is not finished AES module has finished AES_MODE R/W R reserved Description Security module, AES core idle A write access starts the AES operation AT86RF232 AES_CTRL AES_CTRL 131 ...
Page 132
... AT86RF232 132 Bit 6:4 - AES_MODE This register bit sets the AES operation mode. Table 11-6. AES_MODE. Register Bits Value AES_MODE Bit 3 - AES_DIR The register bit AES_DIR sets the AES operation direction, either encryption or decryption. Table 11-7. AES_DIR. Register Bits Value AES_DIR ...
Page 133
... Random Number Generator 11.2.1 Overview 11.2.2 Register Description 8321A–MCU Wireless–10/11 The Atmel AT86RF232 incorporates a two bit truly random number generator by observation of noise. This random number can be used to: Generate random seeds for CSMA-CA algorithm Generate random values for AES key generation The random number is updated every t states ...
Page 134
... The Antenna Diversity implementation is characterized by: Improves signal path robustness between nodes Atmel AT86RF232 self-contained antenna diversity algorithm Direct register based antenna selection Due to multipath propagation effects between network nodes, the receive signal strength may vary and affect the link quality, even for small changes of the antenna location ...
Page 135
... Antenna Diversity Sensitivity Control 8321A–MCU Wireless–10/11 If the Atmel AT86RF232 is not in a receive or transmit state recommended to disable register bit ANT_EXT_SW_EN to reduce the power consumption or avoid leakage current of an external RF switch, especially during SLEEP state. If register bit ANT_EXT_SW_EN = 0, output pins DIG1/DIG2 are pulled-down to digital ground. ...
Page 136
... Register Description AT86RF232 136 Register 0x0A (RX_CTRL): The RX_CTRL register controls the sensitivity of the Antenna Diversity mode. Figure 11-10. Register RX_CTRL. Bit 7 0x0A Read/Write R Reset value 0 Bit 3 0x0A Read/Write R/W R/W Reset value 0 Bit 3:0 - PDT_THRES The register bits PDT_THRES controls the sensitivity of the receiver correlation unit. ...
Page 137
... Antenna Diversity algorithm (ANT_DIV_EN = 1), or according to register bits ANT_CTRL if Antenna Diversity algorithm is disabled. If the Atmel AT86RF232 is not in a receive or transmit state recommended to disable register bit ANT_EXT_SW_EN to reduce the power consumption or avoid leakage current of an external RF switch, especially during SLEEP state. If register bit ANT_EXT_SW_EN = 0, output pins DIG1 and DIG2 are pulled-down to digital ground ...
Page 138
... AT86RF232 138 Bit 1:0 - ANT_CTRL These register bits provide a static control of an Antenna Diversity switch. Table 11-13. ANT_CTRL. Register Bits Value ANT_CTRL Description Mandatory setting for applications not using Antenna Diversity and if autonomous antenna selection is enabled Antenna 0 DIG1 = L DIG2 = H Antenna 1 ...
Page 139
... Interrupt latency 11.4.2 Register Description 8321A–MCU Wireless–10/11 An exact timing of received and transmitted frames is signaled by Atmel AT86RF232 pin 10 (DIG2). A valid PHR reception or start of frame transmission is indicated by a DIG2 posedge. The pin remains high during frame reception or transmission. TX Frame Time Stamping is limited to TX_ARET, whereas the RX Frame Time Stamping is available for all receive modes ...
Page 140
... AT86RF232 140 Bit 6 - IRQ_2_EXT_EN Controls external signaling for time stamping via pin 10 (DIG2). Table 11-14. IRQ_2_EXT_EN. Register Bits Value IRQ_2_EXT_EN 0 (1) 1 Notes: 1. The pin 10 (DIG2) is also active even if the corresponding interrupt event IRQ_2 (RX_START) mask bit in register 0x0E (IRQ_MASK) is set to zero. ...
Page 141
... Wireless–10/11 For time critical applications that want to start reading the frame data as early as possible, the Atmel AT86RF232 Frame Buffer status can be indicated to the microcontroller through a dedicated pin. This pin indicates to the microcontroller if an access to the Frame Buffer is not possible since valid PSDU data are missing. ...
Page 142
... Register Description AT86RF232 142 Register 0x04 (TRX_CTRL_1): The TRX_CTRL_1 register is a multi-purpose register to control various operating modes and settings of the radio transceiver. Figure 11-16. Register TRX_CTRL_1. Bit 7 0x04 reserved IRQ_2_EXT_EN Read/Write R/W R/W Reset value 0 Bit 3 0x04 SPI_CMD_MODE Read/Write R/W R/W Reset value 0 Bit 4 - RX_BL_CTRL The register bit RX_BL_CTRL controls the Frame Buffer Empty Indicator ...
Page 143
... Register Description 8321A–MCU Wireless–10/11 The Atmel AT86RF232 continues the reception of incoming frames as long any receive state. When a frame was successfully received and stored into the Frame Buffer, the following frame will overwrite the Frame Buffer content again. ...
Page 144
... High level output voltage OH V Low level output voltage OL AT86RF232 144 Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied ...
Page 145
... DD Load Min. Typ (1) 250 (1) 500 62.5 (1) 250 (1) 500 250 625 625 750 62.5 (Min.) and t (Min.) increases to 500ns AT86RF232 Max. Unit pF Max. Unit 7.5 MHz 180 (2) Note µs MHz MHz ...
Page 146
... ACC EVM EVM P Harmonics HARM (1) P Spurious Emissions SPUR_TX Note: 1. Complies with EN 300 328/440, FCC-CFR-47 part 15, ARIB STD-66, RSS-210. AT86RF232 146 Test Conditions (unless otherwise stated 3.0V 2445MHz +25°C, Measurement setup see Condition As specified in [1], [2] As specified in [1], [2] As specified in [1], [2] ...
Page 147
... RF (1) 250kb -82dBm RF LO leakage 30 – ≤ 1000MHz >1 – 12.75GHz Sensitivity loss ≤ 2dB Tolerance within gain step Defined as RSSI_BASE_VAL P ≤ RSSI_BASE_VAL RF P ≥ RSSI_BASE_VAL + 84dB RF AT86RF232 Figure 5-1. Min. Typ. Max. Unit -100 dBm -99 dBm dBm ...
Page 148
... All power consumption measurements are performed with CLKM disabled. 12.9 Crystal Parameter Requirements Symbol Parameter f Crystal frequency 0 C Load capacitance L C Static capacitance 0 R Series resistance 1 AT86RF232 148 Test Conditions (unless otherwise stated 3.0V 2445MHz +25°C, Measurement setup see Condition P = +3dBm +0dBm ...
Page 149
... Active Supply Current 13.1.1 P_ON and TRX_OFF states 8321A–MCU Wireless–10/11 The following charts showing each a typical behavior of the Atmel AT86RF232. These figures are not tested during manufacturing. All power consumption measurements are performed with pin 17 (CLKM) disabled, unless otherwise stated. The measurement ...
Page 150
... PLL_ON state AT86RF232 150 Figure 13-2. Current Consumption in TRX_OFF State. 0.4 0,4 0.3 0,3 0.2 0,2 0.1 0,1 0.0 0,0 1.6 1.8 2.0 2.2 1,6 1,8 2,0 2,2 Figure 13-3. Current Consumption in PLL_ON State. 6,0 6.0 5,0 5.0 4,0 4.0 3,0 3.0 2,0 2.0 1.0 1,0 0.0 0,0 1,6 1,8 2,0 2,2 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 2,4 2,6 2,8 3,0 3,2 EVDD [V] EVDD [V] 2,4 2,6 2,8 3,0 3,2 2.4 2.6 2.8 3.0 3.2 EVDD [V] EVDD [V] 70°C 70°C 25°C 25°C 0°C 0°C 3.4 3.6 3.8 3,4 3,6 3,8 70°C 70°C 25°C 25°C 0°C 0°C 3,4 3,6 3,8 3.4 3.6 3.8 8321A–MCU Wireless–10/11 ...
Page 151
... RX_ON state 8321A–MCU Wireless–10/11 Figure 13-4. Current Consumption in RX_ON State – High Sensitivity. 14,0 14.0 12,0 12.0 10.0 10,0 8.0 8,0 6.0 6,0 4.0 4,0 2.0 2,0 0.0 0,0 1.6 1.8 2.0 2.2 1,6 1,8 2,0 2,2 Figure 13-5. Current Consumption in RX_ON State – Reduced Sensitivity. 14,0 14.0 12,0 12.0 10,0 10.0 8,0 8.0 6,0 6.0 4,0 4.0 2.0 2,0 0.0 0,0 1.6 1.8 2.0 2.2 1,6 1,8 2,0 2,2 AT86RF232 2.4 2.6 2.8 3.0 3.2 3.4 2,4 2,6 2,8 3,0 3,2 EVDD [V] EVDD [V] 2.4 2.6 2.8 3.0 3.2 3.4 2,4 2,6 2,8 3,0 3,2 EVDD [V] EVDD [V] 70°C 70°C 25°C 25°C 0°C 0°C 3.6 3.8 3,4 3,6 3,8 70°C 70°C 25°C 25°C 0°C 0°C 3.6 3.8 3,4 3,6 3,8 151 ...
Page 152
... TX_BUSY state AT86RF232 152 Figure 13-6. Current Consumption in TX_BUSY State – Minimum Output Power. 9,0 9.0 8.0 8,0 7,0 7.0 6.0 6,0 5,0 5.0 4,0 4.0 2.0 3,0 2,0 2.0 1,0 1.0 0.0 0,0 1,6 1,8 2,0 2,2 1.6 1.8 2.0 2.2 Figure 13-7. Current Consumption in TX_BUSY State – Output Power 0dBm. 14,0 14.0 12,0 12.0 10,0 10.0 8,0 8.0 6,0 6.0 4,0 4.0 2,0 2.0 0,0 0.0 1,6 1.6 1.8 1,8 2,0 2.0 2.2 2,2 2,4 2,6 2,8 3,0 3,2 2.4 2.6 2.8 3.0 3.2 EVDD [V] EVDD [V] 2.4 2,4 2.6 2,6 2.8 2,8 3.0 3,0 3.2 3,2 3.4 EVDD [V] EVDD [V] 70°C 70°C 25°C 25°C 0°C 0°C 3,4 3,6 3,8 3.4 3.6 3.8 70°C 70°C 25°C 25°C 0°C 0°C 3,4 3.6 3,6 3.8 3,8 8321A–MCU Wireless–10/11 ...
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... SLEEP 8321A–MCU Wireless–10/11 Figure 13-8. Current Consumption in TX_BUSY State – Maximum Output Power. 16,0 16.0 14,0 14.0 12,0 12.0 10.0 10,0 8.0 8,0 6.0 6,0 4.0 4,0 2.0 2,0 0.0 0,0 1,6 1.6 1.8 1,8 2,0 2.0 2.2 2,2 Figure 13-9. Current Consumption in SLEEP. 1,0 1.0 0,9 0.9 0,8 0.8 0,7 0.7 0.6 0,6 0,5 0.5 0.4 0,4 0,3 0.3 0.2 0,2 0,1 0.1 0.0 0,0 1,6 1.6 1.8 1,8 2.0 2,0 2.2 2,2 AT86RF232 2.4 2,4 2.6 2,6 2.8 2,8 3.0 3,0 3.2 3,2 3.4 EVDD [V] EVDD [V] 2.4 2,4 2.6 2,6 2.8 2,8 3.0 3,0 3.2 3,2 EVDD [V] EVDD [V] 70°C 70°C 25°C 25°C 0°C 0°C 3,4 3.6 3,6 3.8 3,8 70°C 70°C 25°C 25°C 0°C 0°C 3.4 3,4 3.6 3,6 3.8 3,8 153 ...
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... State Transition Timing AT86RF232 154 Figure 13-10. Transition Time from EVDD to P_ON (CLKM available). 450,0 450.0 400,0 400.0 350,0 350.0 300,0 300.0 250,0 250.0 200,0 200.0 150,0 150.0 100,0 100.0 50,0 50.0 0.0 0,0 1,6 1,8 2,0 2,2 1.6 1.8 2.0 2.2 Figure 13-11. Transition Time from SLEEP to TRX_OFF (IRQ_4 (AWAKE_END)). 400,0 400.0 350,0 350.0 300,0 300 ...
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... Wireless–10/11 Figure 13-12. Transition Time from TRX_OFF to PLL_ON. 100.0 100,0 90.0 90,0 80.0 80,0 70.0 70,0 60.0 60,0 50.0 50,0 40.0 40,0 30.0 30,0 20.0 20,0 10.0 10,0 0.0 0,0 1.6 1.8 2.0 2.2 1,6 1,8 2,0 2,2 AT86RF232 2.4 2.6 2.8 3.0 3.2 2,4 2,6 2,8 3,0 3,2 EVDD [V] EVDD [V] 70°C 70°C 25°C 25°C 0°C 0°C 3.4 3.6 3.8 3,4 3,6 3,8 155 ...
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... IEEE_ADDR_7 AT86RF232 156 The Atmel AT86RF232 provides a register space of 64 8-bit registers, used to configure, control and monitor the radio transceiver. Note: All registers not mentioned within the following table are reserved for internal use and must not be overwritten. When writing to a register, any reserved bits shall be overwritten only with their reset value ...
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... XAH_CTRL_0 MAX_FRAME_RETRIES 0x2D CSMA_SEED_0 0x2E CSMA_SEED_1 AACK_FVN_MODE 0x2F CSMA_BE 0x36 TST_CTRL_DIGI reserved reserved 8321A–MCU Wireless–10/11 Bit 5 Bit 4 Bit 3 CSMA_SEED_0 AACK_SET_PD AACK_DIS_ACK AACK_I_AM_COORD MAX_BE reserved reserved AT86RF232 Bit 2 Bit 1 Bit 0 MAX_CSMA_RETRIES SLOTTED_OPERATION CSMA_SEED_1 MIN_BE TST_CTRL_DIG Page 166 157 ...
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... AT86RF232 158 The reset values of the Atmel AT86RF232 registers in state P_ON Table 14-2. Note: All reset values in Table 14-2 procedure (/RST = L) as described in selected registers (for example registers 0x01, 0x10, 0x11, 0x30) can differ from that in Table 14-2 ...
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... Frame control field FCS - Frame check sequence FIFO - First in first out FTN - Filter tuning network GPIO - General purpose input output ISM - Industrial, scientific, and medical LDO - Low-drop output LNA - Low-noise amplifier LO - Local oscillator LQI - Link quality indicator LSB - Least significant bit AT86RF232 159 ...
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... AT86RF232 160 MAC - Medium access control MFR - MAC footer MHR - MAC header MISO - SPI Interface: Master input slave output MOSI - SPI Interface: Master output slave input MSB - Most significant bit MSDU - MAC service data unit MPDU - MAC protocol data unit MSK ...
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... Wireless–10/11 XOSC - Crystal oscillator AT86RF232 161 ...
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... AT86RF232-ZX Tray AT86RF232-ZXR Tape & Reel Package Type Description QN 32QN2, 32-lead 5.0 x 5.0mm Body, 0.50mm Pitch, Quad Flat No-lead Package (QFN) Sawn 17 Soldering Information 18 Package Thermal Properties AT86RF232 162 Package Voltage Range QN 1.8V – 3.6V QN 1.8V – 3.6V Note: T&R quantity 5,000. Please contact your local Atmel sales office for more detailed ordering information and minimum quantities ...
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... Package Drawing – 32QN2 8321A–MCU Wireless–10/11 AT86RF232 SYMBOL MIN. NOM. MAX. NOTE 163 ...
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... A.1 - Overview A.2 - Configuration AT86RF232 164 The Atmel AT86RF232 offers a Continuous Transmission Test Mode to support final application / production tests as well as certification tests. Using this test mode the radio transceiver transmits continuously a previously transferred frame (PRBS mode continuous wave signal (CW mode mode two different signal frequencies per channel can be transmitted: ...
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... Enable Continuous Transmission Test Mode – step # 3 W 0x09 Enable PLL_ON state R 0x01 Wait for IRQ_0 (PLL_LOCK) W 0x02 Initiate Transmission, enter BUSY_TX state Perform measurement W 0x00 Disable Continuous Transmission Test Mode Reset AT86RF232 Comment Modulated RF signal Fc – 0.5MHz, CW signal Fc + 0.5MHz, CW signal 165 ...
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... A.3 – Register Description AT86RF232 166 Register 0x36 (TST_CTRL_DIGI): The TST_CTRL_DIG register enables the continuous transmission test mode. Figure 0-1. Register TST_CTRL_DIGI. Bit 7 0x36 Read/Write R/W R/W Reset value 0 Bit 3 0x36 Read/Write R/W R/W Reset value 0 Bit 3:0 - TST_CTRL_DIG The register bits TST_CTRL_DIG with value 0xF enables continuous transmission. ...
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... Appendix B - Errata AT86RF232 Rev. A 8321A–MCU Wireless–10/11 Potential current peak in radio transceiver state SLEEP When leaving active states like receive or transmit immediately towards SLEEP state, a transient current peak of a few µA at DEVDD may occur for a short period of time. Occurance depends on operational parameters as well as load capacitance at pin 29 (AVDD) ...
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... Charged Device Model (CDM). [5] NIST FIPS PUB 197: Advanced Encryption Standard (AES), Federal Information Processing Standards Publication 197, US Department of Commerce/NIST, November 26, 2001 [6] AT86RF232 Software Programming Model [7] IEEE Std 802.15.4™-2011: Low-Rate Wireless Personal Area Networks (WPANs) 8321A–MCU Wireless–10/11 ...
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... Data Sheet Revision History Rev. 8321A–MCU Wireless–10/11 8321A–MCU Wireless–10/11 1. Initial release AT86RF232 169 ...
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... Table of Contents AT86RF232 170 1 Pin-out Diagram .................................................................................. 2 1.1 Pin Descriptions...................................................................................................... 3 1.2 Analog and RF Pins ............................................................................................... 4 1.2.1 Supply and Ground Pins................................................................................................ 4 1.2.2 RF Pins .......................................................................................................................... 4 1.2.3 Crystal Oscillator Pins ................................................................................................... 5 1.2.4 Analog Pin Summary ..................................................................................................... 5 1.3 Digital Pins .............................................................................................................. 6 1.3.1 Driver Strength Settings ................................................................................................ 6 1.3.2 Pull-up and Pull-down Configuration ............................................................................. 6 2 Disclaimer ............................................................................................ 7 3 Overview .............................................................................................. 7 4 General Circuit Description................................................................ 8 5 Application Circuits .......................................................................... 10 5 ...
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... Link Quality Indication (LQI) ................................................................................. 98 8.6.1 Overview ..................................................................................................................... 98 8.6.2 Request an LQI Measurement .................................................................................... 99 8.6.3 Data Interpretation ....................................................................................................... 99 9 Module Description ......................................................................... 100 9.1 Receiver (RX) ..................................................................................................... 100 9.1.1 Overview ................................................................................................................... 100 9.1.2 Frame Receive Procedure ......................................................................................... 100 9.1.3 Configuration ............................................................................................................. 100 9.1.4 Register Description .................................................................................................. 101 9.2 Transmitter (TX) ................................................................................................. 103 9.2.1 Overview ................................................................................................................... 103 9.2.2 Frame Transmit Procedure ........................................................................................ 103 9.2.3 Configuration ............................................................................................................. 103 9.2.4 TX Power Ramping ................................................................................................... 104 AT86RF232 171 ...
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... Automatic Filter Tuning (FTN) ............................................................................ 122 9.8.1 Overview ................................................................................................................... 122 9.8.2 Register Description .................................................................................................. 122 10 Radio Transceiver Usage ............................................................. 123 10.1 Frame Receive Procedure ............................................................................... 123 10.2 Frame Transmit Procedure .............................................................................. 124 11 AT86RF232 Extended Feature Set ............................................... 125 11.1 Security Module (AES) ..................................................................................... 125 11.1.1 Overview ................................................................................................................. 125 11.1.2 Security Module Preparation ................................................................................... 125 11.1.3 Security Key Setup .................................................................................................. 126 11.1.4 Security Operation Modes ....................................................................................... 126 11.1.5 Data Transfer – ...
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... TX_BUSY state ....................................................................................................... 152 13.1.5 SLEEP ..................................................................................................................... 153 13.2 State Transition Timing .................................................................................... 154 14 Register Reference ....................................................................... 156 15 Abbreviations ................................................................................ 159 16 Ordering Information .................................................................... 162 17 Soldering Information ................................................................... 162 18 Package Thermal Properties ........................................................ 162 19 Package Drawing – 32QN2 ........................................................... 163 Appendix A - Continuous Transmission Test Mode ....................... 164 A.1 - Overview .......................................................................................................... 164 A.2 - Configuration.................................................................................................... 164 AT86RF232 173 ...
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... AT86RF232 174 A.3 – Register Description ........................................................................................ 166 Appendix B - Errata ........................................................................... 167 AT86RF232 Rev. A .................................................................................................. 167 References.......................................................................................... 168 Data Sheet Revision History ............................................................. 169 8321A–MCU Wireless–10/11 ................................................................................... 169 Table of Contents ............................................................................... 170 8321A–MCU Wireless–10/11 ...
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... Wireless–10/11 AT86RF232 175 ...