AT86RF232 Atmel Corporation, AT86RF232 Datasheet - Page 129

• Manufacturer Part Number: AT86RF232
• Manufacturer: Atmel Corporation

Specifications of AT86RF232

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 0.25
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -100
• Receive Current Consumption (ma): 11.8
• Transmit Current Consumption (ma): 13.8
• Link Budget (dbm): 103

11.1.5 Data Transfer – Fast SRAM Access
Figure 11-5. Packet Structure – Fast SRAM Access Mode.
MOSI
MISO
Address
MOSI
MISO
Address
8321A–MCU Wireless–10/11
cmd add cfg
stat xx
PHY_STATUS
byte 0 (cmd)
SRAM write
0x83
xx
AES access #0
P0
xx
byte 1 (addr.)
address 0x83
P1
xx
XX
...
...
...
P14
xx
initialization vector is zero. However, for non-compliant usage any other initialization
vector can be used. This operation has to be prepared by the microcontroller.
The ECB and CBC modules including the AES core are clocked with 16MHz. One AES
operation takes t
processing of the data is usually faster than the transfer of the data via the SPI
interface.
To reduce the overall processing time the Atmel AT86RF232 provides a Fast SRAM
access for the address space 0x82 to 0x94.
In contrast to a standard SRAM access, refer to
allows writing and reading of data simultaneously during one SPI access for
consecutive AES operations (AES run).
For each byte P0 transferred to pin 22 (MOSI) for example in “AES access #1”, see
Figure 11-5
clocked out at pin 20 (MISO) with an offset of one byte.
In the example shown in
SRAM
(AES_CTRL_MIRROR) starts the AES operation (“AES run #0”). In the next “AES
access #1” new plaintext data P0 – P15 is written to the SRAM for the second AES run,
in parallel the ciphertext C0 – C15 from the first AES run is clocked out at pin MISO. To
read the ciphertext from the last “AES run #(n)” one dummy “AES access #(n+1)” is
needed.
Note:
Note:
Note:
P15
xx
<AES_CTRL>
0x94
byte 2 (cfg)
start
AES run #0
xx
0x83
XX
within
1. The IEEE 802.15.4-2006 standard MIC algorithm requires CBC mode
1. Byte 19 is the mirrored version of register AES_CTRL on SRAM
2. The SRAM write access always overwrites the previous processing
cmd add cfg
stat xx
(lower part), the previous content of the respective AES register C0 is
encryption only, as it implements a one-way hash function.
address 0x94, see register description AES_CTRL_MIRROR for details.
result.
AES
“AES
0x83
xx
= 23.4µs to execute, refer to
P0[7:0]
byte 3
0x84
XX
AES access #1
P0
xx
access #0”.
Figure 11-5
P1
C0
...
...
...
C13
P14
P1[7:0]
C0[7:0]
byte 4
0x85
P15
C14
the initial plaintext P0 – P15 is written to the
The
0x94
start
C15
AES run #n
...
...
last
Section
cmd add cfg
stat xx
Table
P15[7:0]
C14[7:0]
byte 18
command
0x93
6.2.3, the Fast SRAM access
0x83
xx
7-2. That means that the
AES access #n+1
xx
xx
AT86RF232
<AES_CTRL>
byte 19 (start)
C0
xx
on
C15[7:0]
0x94
...
...
...
address 0x94
C13
xx
(1)
C14
xx
0x94
start
C15
129