AT89LP3240 Atmel Corporation, AT89LP3240 Datasheet
AT89LP3240
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AT89LP3240 Summary of contents
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... Input-Only (Tristate) • Push-pull CMOS Output • Open-drain • Operating Conditions – 2.4V to 3.6V V Voltage Range DD – -40° 85°C Temperature Range – MHz @ 2.4–3.6V ® 51 Products 8-bit Microcontroller with 32K/64K Bytes In-System Programmable Flash AT89LP3240 AT89LP6440 3706C–MICRO–2/11 ...
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... Pin Configurations 1.1 40P6: 40-lead PDIP 1.2 44A: 44-lead TQFP (Top View) MOSI/P1.5 MISO/P1.6 SCK/P1.7 RST/P4.2 RXD/P3.0 TXD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 AT89LP3240/6440 2 T2/P1 VDD T2EX/P1 P0.0/AD0 SDA/P1 P0.1/AD1 SCL/P1 P0.2/AD2 SS/P1 P0.3/AD3 MOSI/P1 P0.4/AD4 MISO/P1 P0.5/AD5 SCK/P1 P0.6/AD6 RST/P4 ...
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... VDD 12 TXD/P3.1 13 INT0/P3.2 14 INT1/P3.3 15 T0/P3.4 16 T1/P3.5 17 MOSI/P1.5 1 MISO/P1.6 2 SCK/P1.7 3 RST/P4.2 4 RXD/P3.0 5 VDD 6 TXD/P3.1 7 INT0/P3.2 8 INT1/P3.3 9 T0/P3.4 10 T1/P3.5 11 NOTE: Bottom pad should be soldered to ground AT89LP3240/6440 39 P0.4/AD4 38 P0.5/AD5 37 P0.6/AD6 36 P0.7/AD7 35 P4.3 34 GND 33 P4.4/ALE 32 P4.5 31 P2.7/AIN3/A15 30 P2.6/AIN2/A14 29 P2.5/AIN1/A13 33 P0.4/AD4 32 P0.5/AD5 31 P0.6/AD6 30 P0.7/AD7 29 P4.3 28 GND 27 P4.4/ALE 26 P4 ...
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... Pin Description Table 1-1. AT89LP3240/6440 Pin Description Pin Number TQFP PLCC PDIP VQFN ...
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... Table 1-1. AT89LP3240/6440 Pin Description Pin Number TQFP PLCC PDIP VQFN ...
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... CPU core that can fetch a single byte from memory every clock cycle. In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instructions to exe- cute in 12 clock cycles. In the AT89LP3240/6440 CPU, standard instructions need only clock cycles providing times more throughput than the standard 8051. Seventy percent of instructions need only as many clock cycles as they have bytes to execute, and most of the remaining instructions require only one additional clock ...
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... Timer 0 and Timer 1 in the AT89LP3240/6440 are enhanced with two new modes. Mode 0 can be configured as a variable 9- to 16-bit timer/counter and Mode 1 can be configured as a 16-bit auto-reload timer/counter. In addition, the timer/counters may each independently drive an 8-bit precision pulse width modulation output. ...
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... XSTK DMEN IAP AT89LP3240/6440 8 lists the fusable options for the AT89LP3240/6440. These options maintain their state Section 25.7 “User Configuration Fuses” on page User Configuration Fuses Description Selects between the High Speed Crystal Oscillator, Low Speed Crystal Oscillator, External Clock or Internal RC Oscillator for the source of the system clock ...
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... Comparison to Standard 8051 The AT89LP3240/6440 is part of a family of devices with enhanced features that are fully binary compatible with the 8051 instruction set. In addition, most SFR addresses, bit assignments, and pin alternate functions are identical to Atmel's existing standard 8051 products. However, due to the high performance nature of the device, some system behaviors are different from those of Atmel's standard 8051 products such as AT89S52 or AT89C2051 ...
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... I/O Ports The I/O ports of the AT89LP3240/6440 may be configured in four different modes. By default all the I/O ports revert to input-only (tristated) mode at power-up or reset. In the standard 8051, all ports are weakly pulled high during power-up or reset. To enable 8051-like ports, the ports must be put into quasi-bidirectional mode by clearing the P1M0, P2M0, P3M0 and P4M0 SFRs ...
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... SIG In addition to the 64K code space, the AT89LP3240/6440 also supports a 256-byte User Signa- ture Array and a 128-byte Atmel Signature Array that are accessible by the CPU. The Atmel Signature Array is initialized with the Device ID in the factory. The second page of the User Sig- nature Array (0180H– ...
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... Internal Data Memory The AT89LP3240/6440 contains 256 bytes of general SRAM data memory plus 128 bytes of I/O memory mapped into a single 8-bit address space. Access to the internal data memory does not require any configuration. The internal data memory has three address spaces: DATA, IDATA and SFR ...
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... The external memory space is accessed with the MOVX instructions. Some internal data memory resources are mapped into portions of the external address space as shown in the CPU can access them. The AT89LP3240/6440 includes 4K bytes of on-chip Extra RAM (EDATA) and 8K bytes of nonvolatile Flash data memory (FDATA). Figure 3-3. ...
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... AT89LP3240/6440 supports up to 52K or 60K bytes of external memory when using the inter- nally mapped memories ...
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... Avoiding unnecessary page erases greatly improves the endurance of the memory. The AT89LP3240/6440 includes 64 data pages of 128 bytes each. One or more bytes in a page may be written at one time. The AT89LP3240/6440 includes a temporary page buffer of 64 bytes, or half of a page ...
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... BOD due to a low voltage condition, the ERR flag will be set. FDATA can always be read regard- less of the BOD state. For more details on using the Flash Data Memory, see the application note titled “AT89LP Flash Data Memory”. FDATA may also be programmed by an external device programmer (See tion 25. on page AT89LP3240/6440 16 FDATA Byte Write DMEN MWEN ...
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... Set by hardware when the voltage on VDD is above the minimum programming voltage. 3.3.4 External Memory Interface The AT89LP3240/6440 uses the standard 8051 external memory interface with the upper address on Port 2, the lower address and data in/out multiplexed on Port 0, and the ALE, RD and WR strobes. The interface may be used in two different configurations depending on which type of MOVX instruction is used to access XDATA ...
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... Note that prior to using the external memory interface, Port 2, WR (P3.6), RD (P3.7) and ALE (P4.4) must be configured as outputs. See is configured automatically to push-pull output mode when outputting address or data and is AT89LP3240/6440 18 shows a hardware configuration for accessing 256-byte blocks of external RAM using External Memory 8-bit Paged Address Mode ...
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... ALE ALES = SFR DPL or Ri OUT P2 P2 SFR S1 S2 CLK ALES = 1 ALE ALES = SFR DPL or Ri OUT P2 P2 SFR AT89LP3240/6440 32 DATA OUT DPH or P2 OUT S3 S4 DATA SAMPLED FLOAT DPH or P2 OUT P0 SFR P2 SFR P0 SFR P2 SFR 19 ...
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... P0 3.4 Extended Stack The AT89LP3240/6440 provides an extended stack space for applications requiring additional stack memory. By default the stack is located in the 256-byte IDATA space of internal data memory. The IDATA stack is referenced solely by the 8-bit Stack Pointer (SP: 81H). Setting the XSTK bit in AUXR enables the extended stack. The extended stack resides in the EDATA space for up to 4KB of stack memory ...
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... In-Application Programming (IAP) The AT89LP3240/6440 supports In-Application Programming (IAP), allowing the program mem- ory to be modified during execution. IAP can be used to modify the user application on the fly or to use program memory for nonvolatile data storage. The same page structure write protocol for FDATA also applies to IAP (See always placed in idle while modifying the program memory ...
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... Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write to these unlisted locations, since they may be used in future products to invoke new features. Table 4-1. AT89LP3240/6440 SFR Map and Reset Values 8 9 0F8H ...
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... Enhanced CPU The AT89LP3240/6440 uses an enhanced 8051 CPU that runs times the speed of standard 8051 devices ( times the speed of X2 8051 devices). The increase in perfor- mance is due to two factors. First, the CPU fetches one instruction byte from the code memory every clock cycle ...
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... AX (E1H) and BX (F7H) hold the higher order bytes. The 16-by-16 bit multiplication is computed through partial products using the AT89LP3240/6440’s 8-bit multiplier. The 32-bit signed product is added to the 40-bit M accumu- lator register. The MAC operation is summarized as follows: All computation is done in signed two’ ...
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... Enhanced Dual Data Pointers The AT89LP3240/6440 provides two 16-bit data pointers: DPTR0 formed by the register pair DPOL and DPOH (82H an 83H), and DPTR1 formed by the register pair DP1L and DP1H (84H and 85H). The data pointers are used by several instructions to access the program or data memories ...
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... MOVC instructions. • In some cases, both data pointers must be used simultaneously. To prevent frequent toggling of DPS, the AT89LP3240/6440 supports a prefix notation for selecting the opposite data pointer per instruction. All DPTR instructions, with the exception of JMP @A+DPTR, when prefixed with an 0A5H opcode will use the inverse value of DPS (DPS) to select the data pointer ...
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... Data Pointer Update The Dual Data Pointers on the AT89LP3240/6440 include two features that control how the data pointers are updated. The data pointer decrement bits, DPD1 and DPD0 in DPCF, configure the INC DPTR instruction to act as DEC DPTR. The resulting operation will depend on DPS as shown in Table 5-3 ...
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... DPTR0 and /DPTR will target DPTR1. When DPS = 1, DPTR will target DPTR1 and /DPTR will target DPTR0. 5.2.2 Data Pointer Operating Modes The Dual Data Pointers on the AT89LP3240/6440 include three additional operating modes that affect data pointer based instructions. These modes are controlled by bits in DSPR. 5.2.2.1 DPTR Redirect The Data Pointer Redirect to B bit, DPRB (DSPR ...
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... Circular Buffers The CBE0 and CBE1 bits in DSPR can configure DPTR0 and DPTR1, respectively, to operate in circular buffer mode. The AT89LP3240/6440 maps circular buffers into two identically sized regions of EDATA/XDATA. These buffers can speed up convolution computations such as FIR and IAR digital filters. The length of the buffers are set by the value of the FIRD (E3H) register for up to 256 entries ...
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... Instruction Set Extensions Table 5-8 AT89LP3240/6440. For more information on the instruction set see Summary” on page “Instruction Set Extensions” on page Table 5-8. Opcode • The /DPTR instructions provide support for the dual data pointer features described above (See • ...
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... Crystal Oscillator Connections Optional 1. C1/C2 = 5–15 pF for Crystals = 5–15 pF for Ceramic Resonators R1 = 4–5 MΩ AT89LP3240/6440 Table 6-1. See 37) Selected Clock Source High Speed Crystal Oscillator (f > 500 kHz) Low Speed Crystal Oscillator (f ≤ 100 kHz) External Clock on XTAL1 Internal 8 MHz RC Oscillator ...
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... System Clock Out When the AT89LP3240/6440 is configured to use either an external clock or the internal RC oscillator, the system clock divided by 2 may be output on XTAL2 (P4.1). The clock out feature is enabled by setting the COE bit in CLKREG. For example, setting COE = “1” when using the internal oscillator will result in a 4.0 MHz (± ...
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... Reset During reset, all I/O Registers are set to their initial values, the port pins are tristated, and the program starts execution from the Reset Vector, 0000H. The AT89LP3240/6440 has five sources of reset: power-on reset, brown-out reset, external reset, watchdog reset, and software reset ...
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... Brown-out Reset or when waking up from Power-down during internally timed mode. The start-up delay should be selected to provide enough settling time for V source. The device operating environment (supply voltage, frequency, temperature, etc.) must AT89LP3240/6440 34 Power-on Reset Sequence (BOD Disabled) V ...
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... SUT Fuse 1 7.2 Brown-out Reset The AT89LP3240/6440 has an on-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level V is nominally 2.0V. The purpose of the BOD is to ensure that if V speed, the system will gracefully enter reset without the possibility of errors induced by incorrect execution ...
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... WDTOVF and SWRST to flag an error. 8. Power Saving Modes The AT89LP3240/6440 supports two different power-reducing modes: Idle and Power-down. These modes are accessed through the PCON register. Additional steps may be required to achieve the lowest possible power consumption while using these modes. ...
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... The interrupt pin need not remain low for the entire time-out period. 3706C–MICRO–2/11 PWDEX POF GF1 can also wake up the device. The GPI pin must be enabled in GPIEN 7-0 AT89LP3240/6440 Reset Value = 000X 0000B GF0 PD IDL has been DD Figure Table 7-1 on page 8-1 ...
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... Brown-out Detector If the Brown-out Detector is not needed by the application, this module should be turned off. If the Brown-out Detector is enabled by the BOD Enable Fuse, it will be enabled in all modes except Power-down. See AT89LP3240/6440 38 Interrupt Recovery from Power-down (PWDEX = 0) t SUT Interrupt Recovery from Power-down (PWDEX = 1) ...
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... IRC is the system clock source) and when the internal reference is disabled (IREF = 0). The DADC must always be disabled before entering power-down. 9. Interrupts The AT89LP3240/6440 provides 12 interrupt sources: two external interrupts, three timer inter- rupts, a serial port interrupt, an analog comparator interrupt, a general-purpose interrupt, a compare/capture interrupt, a two-wire interrupt, an ADC interrupt and an SPI interrupt. These interrupts and the system reset each have a separate program vector at the start of the program memory space ...
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... TWSR and respond accordingly before the bit is cleared by software. All of the bits that generate interrupts can be set or cleared by software, with the same result as though they had been set or cleared by hardware. That is, interrupts can be generated and pending interrupts can be canceled in software. AT89LP3240/6440 40 3706C–MICRO–2/11 ...
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... Interrupt Vector Addresses Source RST or POR or BOD IE0 TF0 IE1 TF1 TF2 or EXF2 CFA or CFB GPIF 7-0 T2CCF 3-0 SPIF or MODF or TXE ADIF TWIF AT89LP3240/6440 Vector Address 0000H 0003H 000BH 0013H 001BH 0023H 002BH 0033H 003BH 0043H 004BH 0053H 005BH 41 ...
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... EC Comparator Interrupt Enable ET2 Timer 2 Interrupt Enable ES Serial Port Interrupt Enable ET1 Timer 1 Interrupt Enable EX1 External Interrupt 1 Enable ET0 Timer 0 Interrupt Enable EX0 External Interrupt 0 Enable . AT89LP3240/6440 42 and Figure 9-2. 5 LCALL 1st ISR Instr. 6 RETI MAC AB ET2 ES ET1 5 4 ...
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... ADC Interrupt Priority Low 3706C–MICRO–2/11 – ETWI EADC PT2 PS PT1 – PTWI PADC AT89LP3240/6440 Reset Value = xxxx x000B ESPI ECC EGP Reset Value = 0000 0000B PX1 PT0 PX0 Reset Value = 0xxx x000B PSP PCC PGP 2 ...
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... PTWH Two-Wire Interface Interrupt Priority High PADH ADC Interrupt Priority High PSPH Serial Peripheral Interface Interrupt Priority High PCCH Compare/Capture Array Interrupt Priority High PGPH General-purpose Interrupt 0 Priority High AT89LP3240/6440 44 PT2H PSH PT1H – PTWH PADH ...
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... I/O Ports The AT89LP3240/6440 can be configured for between 35 and 38 I/O pins. The exact number of I/O pins available depends on the clock and reset options as shown in Table 10-1. Clock Source External Crystal or Resonator External Clock Internal RC Oscillator 10.1 Port Configuration All port pins on the AT89LP3240/6440 may be configured to one of four modes: quasi-bidirec- tional (standard 8051 port outputs), push-pull output, open-drain output, or input-only ...
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... Schmitt-triggered input for improved input noise rejection. The input circuitry of P3.2, P3.3, P4.2, P4.0 and P4.1 is not disabled during Power-down (see fore these pins should not be left floating during Power-down when configured in this mode. Figure 10-2. Input Only AT89LP3240/6440 46 1 Clock Delay (D Flip-Flop) From Port ...
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... Register 3706C–MICRO–2/11 Input Data Figure 10-4. The input circuitry of P3.2, P3.3, P4.0, P4.1 and P4.2 is not Figure 10-3) and therefore these pins should not be left float- From Port Register Input Data V Input Data PWD AT89LP3240/6440 Port Pin Port Pin PWD Figure 10-5. CC Port Pin . The pull ...
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... Port Analog Functions The AT89LP3240/6440 incorporates two analog comparators and an 8-channel analog-to-digital converter. In order to give the best analog performance and minimize power consumption, pins that are being used for analog functions must have both their digital outputs and digital inputs disabled ...
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... Port Alternate Functions Most general-purpose digital I/O pins of the AT89LP3240/6440 share functionality with the vari- ous I/Os needed for the peripheral units. Alternate functions are connected to the pins in a logic AND fashion. In order to enable the alternate function on a port pin, that pin must have a “1” in its corresponding port register bit, otherwise the input/output will always be “ ...
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... Table 10-6. Port Pin P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.2 P4.6 P4.7 AT89LP3240/6440 50 Port Pin Alternate Functions Configuration Bits PxM0.y PxM1.y P1M0.2 P1M1.2 P1M0.3 P1M1.3 P1M0.4 P1M1.4 P1M0.5 P1M1.5 P1M0.6 P1M1.6 P1M0.7 P1M1.7 P2M0.0 P2M1.0 P2M0.1 P2M1.1 P2M0.2 P2M1.2 P2M0.3 P2M1.3 P2M0.4 P2M1.4 P2M0.5 P2M1.5 P2M0.6 P2M1.6 P2M0.7 P2M1.7 P3M0.0 P3M1 ...
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... Enhanced Timer 0 and Timer 1 with PWM The AT89LP3240/6440 has two 16-bit Timer/Counters, Timer 0 and Timer 1, with the following features: • Two 16-bit timer/counters with 16-bit reload registers • Two independent 8-bit precision PWM outputs with 8-bit prescalers • UART or SPI baud rate generation using Timer 1 • ...
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... RH1/RL1 and the overflow flag bit in TCON is set. See gives the full 16-bit timer period compatible with the standard 8051. Mode 1 operation is the same for Timer/Counter 0. AT89LP3240/6440 52 shows the Mode 0 operation as it applies to Timer 1 in 13-bit mode. As the count Mode 0: ...
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... C Pin TR1 GATE1 INT0 Pin RH1/RL1 are not required by Timer 1 during Mode 2 and may be used as temporary storage registers. Figure 11-4. TL0 uses the Timer 0 control bits: C/T, GATE0, TR0, INT0, and TF0. TH0 AT89LP3240/6440 RL1 RH1 (8 Bits) (8 Bits) Reload TL1 TH1 TF1 ...
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... Mode 3 is for applications requiring an extra 8-bit timer or counter. With Timer 0 in Mode 3, the AT89LP3240/6440 can appear to have four Timer/Counters. When Timer Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3. In this case, Timer 1 can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt ...
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... Auto Reload Mode. TH0 holds a value which is reloaded into 8-bit Timer/Counter 0 TL0 each time it overflows. Split Timer Mode. TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 1 control bits. TH0 is an 8-bit timer only controlled by Timer 1 control bits. AT89LP3240/6440 Reset Value = 0000 0000B C/T0 T0M0 T0M1 2 ...
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... PSC00 11.5 Pulse Width Modulation On the AT89LP3240/6440, Timer 0 and Timer 1 may be independently configured as 8-bit asymmetrical (edge-aligned) pulse width modulators (PWM) by setting the PWM0EN or PWM1EN bits in TCONB, respectively. In PWM Mode the generated waveform is output on the timer's input pin T1. Therefore, C/Tx must be set to “0” when in PWM mode and the T0 (P3 ...
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... Mode 0: Duty Cycle % ÷TPS OSC Control TR1 GATE1 f = out Mode 1: Duty Cycle % 58). Timer 1 in PWM Mode 2 is identical to Timer 0. PWM Mode 2 can be Oscillator Frequency ------------------------------------------------------ - Mode × out 2 AT89LP3240/6440 Oscillator Frequency 1 × ------------------------------------------------------ - -------------------- - PSC0 + 1 TPS + 1 × 256 2 RH0 × ----------- - 100 = 256 RH1 ...
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... Figure 11-7. Timer/Counter 1 PWM Mode 1 GATE1 INT1 Pin Figure 11-8. Timer/Counter 1 PWM Mode 2 Note: Figure 11-9. PWM Mode 2 Waveform AT89LP3240/6440 58 ÷TPS OSC Control TR1 ÷TPS OSC Control TR1 GATE1 INT1 Pin {RH0 & RL0}/{RH1 & RL1} are not required by Timer 0/Timer 1 during PWM Mode 2 and may be used as temporary storage registers ...
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... TH0. PWM Mode 3 is for applications requiring a single PWM channel and two timers, or two PWM channels and an extra timer or counter. With Timer 0 in PWM Mode 3, the AT89LP3240/6440 can appear to have four Timer/Counters. When Timer PWM Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3 ...
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... Enhanced Timer 2 The AT89LP3240/6440 includes a 16-bit Timer/Counter 2 with the following features: • 16-bit timer/counter with one 16-bit reload/capture register • One external reload/capture input • Up/Down counting mode with external direction control • UART baud rate generation • Output-pin toggle on timer overflow • ...
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... → → → → → AT89LP3240/6440 Table Reset Value = 0000 0000B TR2 C/T2 CP/RL2 2 1 Reset Value = 0000 0000B T2CM0 T2OE DCEN 2 1 → → → → → → → ...
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... T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 and TF2 bits can generate an interrupt. Capture mode is illustrated in The Timer 2 overflow rate in Capture mode is given by the following equation: AT89LP3240/6440 62 Phase Mode Disabled, all channels active 2-phase output on channels A & ...
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... X X Up-Down Up-Down shows Timer 2 automatically counting up when DCEN = 0 and T2CM Time-out Period = 01B. In this mode Timer 2 counts up to TOP, the 16-bit value in RCAP2H and 1-0 AT89LP3240/6440 TL2 TH2 TF2 OVERFLOW RCAP2L RCAP2H TIMER 2 INTERRUPT EXF2 Table 12-5. Behavior → Up ...
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... Setting DCEN = 1 enables Timer 2 to count up or down, as shown in the T2EX pin controls the direction of the count (if EXEN2 = 1). A logic 1 at T2EX makes Timer 2 count up. When T2CM also causes BOTTOM, the 16-bit value in RCAP2H and RCAP2L reloaded into the timer AT89LP3240/6440 64 Time-out Period Figure 12-3 ...
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... Changes to the count direction may result in longer or shorter periods between time-outs. Figure 12-5. Timer 2 Diagram: Auto-Reload Mode (T2CM ÷TPS 3706C–MICRO–2/11 AT89LP3240/6440 = 01B, the timer will overflow at TOP and set the TF2 bit. This 1-0 Figure = 00B, DCEN = 1) ...
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... EXF2 bit to determine if TF2 was set at TOP or MIN. These count modes are provided to support variable precision symmetrical PWM in the CCA. DCEN has no effect when using dual slope operation. The Timer 2 overflow rate for this mode is given in the following equation: Auto-Reload Mode: DCEN = 0, T2CM = 10B AT89LP3240/6440 66 T2CM = 00B, DCEN = 1 1-0 ...
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... RCAP2L) to (TH2, TL2). Thus when Timer use as a baud rate gen- 3706C–MICRO–2/11 MAX TOP MIN EXF2 MAX TOP MIN Modes 1 and 3 Baud Rates Modes 1, 3 T2CM = 00B = -------------------------------------------------------------------------------------------------------------------------------- - 16 Baud Rate Modes 1, 3 T2CM = 01B = ------------------------------------------------------------------------------------------------------------------ - 16 Baud Rate AT89LP3240/6440 T2CM = 10B 1-0 T2CM = 11B 1-0 Figure 12-8. Timer 2 Overflow Rate = ----------------------------------------------------------- - 16 Oscillator Frequency × × TPS + ...
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... Timer 2 is used as a baud-rate generator possible to use Timer baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L. AT89LP3240/6440 68 C/ TL2 ...
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... T2 PIN T2EX PIN 13. Compare/Capture Array The AT89LP3240/6440 includes a four channel Compare/Capture Array (CCA) that performs a variety of timing operations including input event capture, output compare waveform generation and pulse width modulation (PWM). Timer 2 serves as the time base for the four 16-bit com- pare/capture modules. The CCA has the following features: • ...
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... T2CCH between T2CCL writes. Every write to T2CCL will use the last value of T2CCH for the upper data byte not possible to write to the data register of a channel config- ured for capture mode. The configuration bits for each channel are stored in the CCCx registers accessible through T2CCC. See AT89LP3240/6440 70 RCAP2L ÷TPS C/ ...
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... C – T2CCH, T2CCL and T2CCC access data and control for Channel C D – T2CCH, T2CCL and T2CCC access data and control for Channel D T2CCD.13 T2CCD.12 T2CCD. T2CCD.5 T2CCD.4 T2CCD AT89LP3240/6440 Reset Value = xxxx xx00B — T2CCA.1 T2CCA Reset Value = 0000 0000B T2CCD.10 T2CCD.9 T2CCD ...
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... A diagram of a CCA channel in capture mode is shown in Figure 13-2. CCA Capture Mode Diagram (P2.x) CCx Each CCA channel has an associated external capture input pin: CCA (P2.0), CCB (P2.1), CCC (P2.2) and CCD (P2.3). External capture events are always edge-triggered and can be selected AT89LP3240/6440 72 – – CCFD ...
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... Down = 1) at the time of the event will be captured into the channel’s CDIRx bit in CCCx. CTCx must be cleared to 0 for all channels if Timer 2 is operating in Baud Rate mode or errors may occur in the serial communication. 3706C–MICRO–2/11 AT89LP3240/6440 = 1xB), the count 1-0 73 ...
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... All writes/reads to/from T2CCC will access channel X as currently selected by T2CCA.The control registers for the remain- ing unselected channels are not accessible. 2. Analog Comparator A events are determined by the CMA 3. Analog Comparator B events are determined by the CMB 4. Asymmetrical versus Symmetrical PWM is determined by the Timer 2 Count Mode. See AT89LP3240/6440 74 – CTCx CCMx ...
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... See PWM operation. 3706C–MICRO–2/11 00H 00H TL2 TH2 CTCx = CCxL CCxH CCCx T2CCL shadow T2CCC T2CCH bits in CCCx determine what action is taken when a 2-0 AT89LP3240/6440 Figure CCx (P2.x) CxM 2-0 CCFx Interrupt CIENx Section 13.4 on page 77 for more details of 13-3. 75 ...
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... More com- plex waveforms are achieved by changing the TOP value and the compare values more frequently. AT89LP3240/6440 76 CP/RL2 = 0, T2CM {CCAH,CCAL} {CCBH,CCBL} ...
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... PWMs are fixed at 8-bit precision regardless of frequency. Figure 13-7. CCA PWM Mode Diagram 3706C–MICRO–2/11 CP/RL2 = 0, T2CM {CCAH,CCAL} {CCBH,CCBL} CCA CCB TL2 TH2 = shadow shadow CCxL CCxH CCCx T2CCL shadow T2CCC T2CCH AT89LP3240/6440 = 10B, DCEN = 0 1-0 = 10xB enables PWM 2-0 Figure 13-7. The PWM polarity CCx (P2.x) CxM 2-0 CCFx Interrupt CIENx 77 ...
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... CCxH), and set at the down-count compare match. In inverting mode, the output CCx is set on the up-count compare match between Timer 2 and the data register, and cleared at the down-count compare match. The resulting symmetrical PWM output waveform is AT89LP3240/6440 78 Figure 13-8. The timer counts up from BOTTOM to TOP and then restarts from BOT- ...
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... Symmetrical PWM operates in phase and frequency correct mode. In 1-0 Figure 13-10 because the up and down count compare values are identical. The = 11B the Symmetrical PWM operates in phase correct mode. In this mode the 1-0 Figure 13-11 because the up and down count compare values may not be identical. AT89LP3240/6440 1 × -------------------- - , } TPS + ...
Page 80
... Multi-Phasic PWM The PWM channels may be configured to provide multi-phasic alternating outputs by the PHS bits in T2MOD. The AT89LP3240/6440 provides 1 out out out of 4 and 2 out of 4 phase modes (See CCD are connected to a one-hot shift register that selectively enables and disables the outputs ...
Page 81
... C D PHS = 010B PHS = 011B CCA CCB CCC CCD PHS = 010B, CCB disabled AT89LP3240/6440 Behavior PHSD = 1 → → → → → → → → → → → → → → → → ...
Page 82
... CCC CCD 14. External Interrupts The INT0 (P3.2) and INT1 (P3.3) pins of the AT89LP3240/6440 may be used as external inter- rupt sources. The external interrupts can be programmed to be level-activated or transition- activated by setting or clearing bit IT1 or IT0 in Register TCON. If ITx = 0, external interrupt x is triggered by a detected low at the INTx pin. If ITx = 1, external interrupt x is edge-triggered. In this mode if successive samples of the INTx pin show a high in one cycle and a low in the next cycle, interrupt request flag IEx in TCON is set ...
Page 83
... CLK AT89LP3240/6440 Figure 15-1. The pins of Port 1 are sampled every GPIF Interrupt ...
Page 84
... P1.x disabled 1 = interrupt for P1.x enabled . Table 15-4. – General-purpose Interrupt Flag Register GPIF GPIF = 9DH Not Bit Addressable GPIF7 GPIF6 Bit 7 6 GPIF interrupt on P1.x inactive 1 = interrupt on P1.x active. Must be cleared by software. AT89LP3240/6440 84 GPMOD5 GPMOD4 GPMOD3 GPLS5 GPLS4 GPLS3 GPIEN5 GPIEN4 ...
Page 85
... Serial Interface (UART) The serial interface on the AT89LP3240/6440 implements a Universal Asynchronous Receiver/Transmitter (UART). The UART has the following features: • Full-duplex Operation • Data Bits • Framing Error Detection • Multiprocessor Communication Mode with Automatic Address Recognition • Baud Rate Generator Using Timer 1 or Timer 2 • ...
Page 86
... Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the RI other modes, in any serial reception (except see SM2). Must be cleared by software. Notes: 1. SMOD0 is located at PCON. oscillator frequency. The baud rate depends on SMOD1 (PCON.7). osc AT89LP3240/6440 86 See “Automatic Address Recognition” on page 97. SM2 REN TB8 5 4 ...
Page 87
... Baud Rate SMOD1 Modes Oscillator Frequency × ------------------- - -------------------------------------------------------- - = [ 32 Baud Rate lists commonly used baud rates and how they can be obtained from Timer 1. AT89LP3240/6440 × Oscillator Frequency 4 × Oscillator Frequency 32 × (Timer 1 Overflow Rate) × (Timer 1 Overflow Rate) 1 × -------------------- - [ ( ...
Page 88
... RCAP2H and RCAP2L, which are preset by software. In this case, the baud rates in Modes 1 and 3 are determined by Timer 2’s overflow rate according to the following equation:. Table 16-3 Table 16-3. Baud Rate 62.5K 19.2K 9.6K 4.8K 2.4K 1.2K 137.5 AT89LP3240/6440 88 Commonly Used Baud Rates Generated by Timer 1 (TPS = 0000B) f (MHz) SMOD1 OSC 11.059 11.059 11.059 11 ...
Page 89
... High Negative edge of clock 0 Low While clock is low 1 Low Negative edge of clock AT89LP3240/6440 shows a simplified functional diagram of Table 16-4 lists the baud rate options for Mode 0. Figure 16-2. The SM2 bit determines the Data Changed Data Sampled Positive edge of clock Positive edge of clock ...
Page 90
... TIMER 1 OVERFLOW f osc 1 0 TB8 ÷2 ÷ SMOD1 WRITE TO SBUF SEND SHIFT RXD (DATA OUT) TXD (SHIFT CLOCK) TI WRITE TO SCON (CLEAR RI) RI RECEIVE SHIFT RXD (DATA IN) TXD (SHIFT CLOCK) AT89LP3240/6440 90 INTERNAL BUS “1“ INTERNAL BUS SM2 3706C–MICRO–2/11 ...
Page 91
... MOV R7 << msb(ACC) XCH A, R6 RRC A ; msb(ACC) >> B XCH A, R6 DJNZ R7, REVRS AT89LP3240/6440 ...
Page 92
... On receive, the stop bit goes into RB8 in SCON. In the AT89LP3240/6440, the baud rate is determined either by the Timer 1 overflow rate, the TImer 2 overflow rate, or both. In this case one timer is for transmit and the other is for receive. ...
Page 93
... RX CLOCK SEND TI TI SERIAL PORT ÷16 LOAD RX CLOCK RI SBUF START RX CONTROL SHIFT 1FFH BIT DETECTOR INPUT SHIFT REG. (9 BITS) LOAD SBUF SBUF READ SBUF INTERNAL BUS AT89LP3240/6440 TXD SHIFT D6 D7 STOP BIT STOP BIT 93 ...
Page 94
... SBUF. One bit time later, whether the above conditions were met or not, the unit continues look- ing for a 1-to-0 transition at the RXD input. Note that the value of the received stop bit is irrelevant to SBUF, RB8, or RI. AT89LP3240/6440 94 show a functional diagram of the serial port in Modes 2 and 3. The ...
Page 95
... Figure 16-5. Serial Port Mode 2 CPU CLOCK SMOD1 1 SMOD1 0 3706C–MICRO–2/11 AT89LP3240/6440 INTERNAL BUS INTERNAL BUS 95 ...
Page 96
... CLOCK WRITE TO SBUF SEND DATA SHIFT D0 D1 TXD START BIT TI STOP BIT GEN ÷16 RESET RX CLOCK RXD START BIT BIT DETECTOR SAMPLE TIMES SHIFT RI AT89LP3240/6440 96 INTERNAL BUS TB8 SBUF CL ZERO DETECTOR STOP BIT SHIFT DATA START TX CONTROL ÷16 RX CLOCK SEND TI ...
Page 97
... Both slaves can be selected at the same time by an address which has bit (for slave 0) and bit (for slave 1). Thus, both could be addressed with 1100 0000. 3706C–MICRO–2/11 SADDR = 1100 0000 SADEN = 1111 1101 Given = 1100 00X0 SADDR = 1100 0000 SADEN = 1111 1110 Given = 1100 000X AT89LP3240/6440 97 ...
Page 98
... Enhanced Serial Peripheral Interface The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT89LP3240/6440 and peripheral devices or between multiple AT89LP3240/6440 devices, including multiple masters and slaves on a single bus. The SPI includes the following features: • Full-duplex, 3-wire or 4-wire Synchronous Data Transfer • ...
Page 99
... TSCK Divider ÷4/÷8/÷32/÷64 SPI Clock (Master) Select MSTR SPE SPI Control 8 SPI Status Register 8 SPI Interrupt Internal Request Data Bus AT89LP3240/6440 LSB S 8-bit Shift Register Read Data Buffer Write Data Buffer Clock S Logic M SPI Control Register 8 Figure MISO P1 ...
Page 100
... Master Operation An SPI master device initiates all data transfers on the SPI bus. The AT89LP3240/6440 is con- figured for master operation by setting MSTR = 1 in SPCR. Writing to the SPI data register (SPDR) while in master mode loads the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer is moved to the shift register ...
Page 101
... Slave Operation When the AT89LP3240/6440 is not configured for master operation, MSTR = 0, it will operate as an SPI slave. In slave mode, bytes are shifted in through MOSI and out through MISO by a mas- ter device controlling the serial clock on SCK. When a byte has been transferred, the SPIF flag is set to “ ...
Page 102
... Please refer to figure on SPI clock phase and polarity control. Clock phase. The CPHA bit together with the CPOL bit controls the clock and data relationship between master and CPHA slave. Please refer to figure on SPI clock phase and polarity control. AT89LP3240/6440 102 SPI Pin Configuration and Behavior when SPE = 1 Mode ...
Page 103
... T1OVF f /32 T1OVF f /64 T1OVF SPD5 SPD4 SPD3 MODF TXE – AT89LP3240/6440 , is as follows: OSC. Reset Value = 00H (after cold reset) unchanged (after warm reset) SPD2 SPD1 SPD0 Reset Value = 0000 X000B SSIG DISSO ENH 103 ...
Page 104
... Figure 17-4. SPI Transfer Format with CPHA = 1 SCK CYCLE # (FOR REFERENCE) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (FROM MASTER) MISO (FROM SLAVE) SS (TO SLAVE) Note: *Not defined but normally LSB of previously transmitted character. AT89LP3240/6440 104 Figures 17-3 and 17-4. To prevent glitches on SCK from disrupting the MSB ...
Page 105
... The number of devices that can be connected to the bus is only limited by the bus capacitance limit of 400 pF and the 7-bit slave address space. 3706C–MICRO–2/11 Figure 18-1 Device 1 Device 3 Device 2 Figure 18-1, both bus lines are connected to the positive supply voltage through AT89LP3240/6440 shows a typical 2-wire bus configuration. Any V CC ........ Device 105 ...
Page 106
... When a slave recognizes that it is being addressed, it should acknowledge by pulling SDA low in the ninth SCL (ACK) cycle. If the addressed Slave is busy, or for some other reason can not service the Mas- AT89LP3240/6440 106 SDA ...
Page 107
... Figure 18-5. Data Packet Format Aggregate SDA from Transmitter SDA from Receiver SCL from 3706C–MICRO–2/11 Addr MSB 1 START Data MSB SDA Master 1 2 SLA+R/W AT89LP3240/6440 Addr LSB R Data LSB ACK Data Byte ACK 9 STOP, REPEATED START, or Next Data Byte ...
Page 108
... Note that all masters listen to the SCL line, effectively starting to count their SCL high and low Time-out periods when the combined SCL line goes high or low, respectively. AT89LP3240/6440 108 shows a typical data transmission. Note that several data bytes can be transmitted ...
Page 109
... A REPEATED START and a STOP condition. 3706C–MICRO–2/11 TA low Line TB Masters Start Counting Low Period START SDA from Master A SDA from M SDA Line SCL Line AT89LP3240/6440 TA high TB low high Masters Start Counting High Period Master A Loses Arbitration, SDA SDA A 109 ...
Page 110
... TWI Bit Rate Register (TWBR). Slave operation does not depend on the Bit Rate setting, but the CPU clock frequency in the slave must be at least 16 times higher than the SCL frequency. Note that slaves may prolong the SCL low period, thereby reducing the AT89LP3240/6440 110 SCL ...
Page 111
... After the TWI has received a data byte. • After a STOP or REPEATED START has been received while still addressed as a Slave. • When a bus error has occurred due to an illegal START or STOP condition. 3706C–MICRO–2/11 AT89LP3240/6440 System Clock SCL frequency = --------------------------------------------- - × ...
Page 112
... Symbol Function TWA Two-wire Interface Slave Address. The TWI will only respond to slave addresses that match this 7-bit address. 6-0 General Call Enable. Set to enable General Call address (00h) recognition. Clear to disable General Call address GC recognition. AT89LP3240/6440 112 STA STO TWIF ...
Page 113
... TWD5 TWD4 TWD3 TWB5 TWB4 TWB3 simple example of how the application can interface to the TWI hardware. In AT89LP3240/6440 Reset Value = 1111 1111B TWD2 TWD1 TWD0 Reset Value = 0000 0000B TWB2 TWB1 TWB0 ...
Page 114
... TWCR, instructing the TWI hardware to transmit the data packet present in TWDR. Which value to write is described later on. However important that the TWIF bit is cleared in the value written. The TWI will not start any operation as AT89LP3240/6440 114 5. Check TWSR to see if SLA+W was sent and ACK received ...
Page 115
... These figures contain the following abbreviations: S: START condition Rs: REPEATED START condition R: Read bit (high level at SDA) W: Write bit (low level at SDA) A: Acknowledge bit (low level at SDA) A: Not acknowledge bit (high level at SDA) Data: 8-bit data byte P: STOP condition 3706C–MICRO–2/11 AT89LP3240/6440 115 ...
Page 116
... After a repeated START condition (status 10h) the Two-wire Serial Interface can access the same slave again new slave without transmitting a STOP condition. Repeated START enables the master to switch between slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus. AT89LP3240/6440 116 to Figure 18-14, circles are used to indicate that the TWIF flag is set ...
Page 117
... No actio action action AT89LP3240/6440 AA Next Action Taken by TWI Hardware SLA+W will be transmitted; X ACK or NOT ACK will be received SLA+W will be transmitted; X ACK or NOT ACK will be received SLA+R will be transmitted; X Logic will switch to Master Receiver mode Data byte will be transmitted and ACK or NOT ...
Page 118
... In the Master Receiver mode, a number of data bytes are received from a slave transmitter. In order to enter a Master mode, a START condition must be transmitted. The format of the follow- ing address packet determines whether Master Transmitter or Master Receiver mode entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered. AT89LP3240/6440 118 ...
Page 119
... Read data byte Read data byte AT89LP3240/6440 AA Next Action Taken by TWI Hardware SLA+R will be transmitted; ACK or NOT ACK X will be received SLA+R will be transmitted; ACK or NOT ACK X will be received SLA+W will be transmitted; Logic will switch to X Master Transmitter mode ...
Page 120
... The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a master. If the LSB is set, the TWI will respond to the general call address (00h), otherwise it will ignore the general call address.: TWCR Value AT89LP3240/6440 120 ...
Page 121
... Read data byte Read data byte AT89LP3240/6440 AA Next Action Taken by TWI Hardware Data byte will be received and NOT ACK will be 0 returned Data byte will be received and ACK will be 1 returned Data byte will be received and NOT ACK will be ...
Page 122
... Figure 18-13. Format and States in Slave Receiver Mode Reception of the own S slave address and one or more data bytes. All are acknowledged Last data byte received is not acknowledged AT89LP3240/6440 122 Arbitration lost as master and addressed as slave Read data byte Read data byte ...
Page 123
... From slave to master 3706C–MICRO–2/11 SLA R A DATA A8h A B0h DATA A n AT89LP3240/6440 A DATA A B8h C0h A C8h Any number of data bytes and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the Two-wire Serial Bus. The prescaler bits are zero or masked to zero Table 18-9 ...
Page 124
... Data byte in TWDR has C0h been transmitted; NOT ACK has been received Last data byte in TWDR has C8h been transmitted (AA = “0”); ACK has been received AT89LP3240/6440 124 Application Software Response To TWCR To/from TWDR STA STO TWIF Load data byte ...
Page 125
... Application Software Response To TWCR To/from TWDR STA STO TWIF No action No action No action AT89LP3240/6440 Table AA Next Action Taken by TWI Hardware Wait or proceed current transfer Only the internal hardware is affected, no STOP X condition is sent on the bus. In all cases, the bus is released and STO is cleared. 18-10. 125 ...
Page 126
... Figure 18-15. Combining Several TWI Modes to Access a Serial EEPROM START 19. Dual Analog Comparators The AT89LP3240/6440 provides two analog comparators. The analog comparators have the fol- lowing features: • Internal 3-level Voltage Reference (1.2V, 1.3V, 1.4V) • Four Shared Analog Input Channels – Configure as Multiple Input Window Comparator • ...
Page 127
... ACSRA and ACSRB. When changing the analog 1-0 1 Disable comparator interrupts ACSRA, #0DFh ; Clear CONA to disconnect COMP A ; Modify CSA or RFA bits ACSRA, #020h ; Set CONA to connect COMP A ACSRA, #0EFh ; Clear any spurious interrupt EC ; Re-enable comparator interrupts AT89LP3240/6440 48. The flags may be 2-0. Figure 20-3. An analog source 127 ...
Page 128
... Therefore, after the initial edge event, the interrupt may occur between 1 and 2 time-out periods later. See flows, i.e. CxC be accepted as an edge event. Figure 19-3. Negative Edge with Debouncing Example Comparator Out Timer 1 Overflow AT89LP3240/6440 128 kΩ AINn C ...
Page 129
... A CMPA - + A CMPA - + AIN3 CMPA AIN2 CSB = 11 RFB = 00 + AIN3 CMPA AREF CSB = 11 RFB = 10 AT89LP3240/6440 f. 2-channel window comparator with external reference CMPB - AIN2 B + AIN0 AIN3 + A - AIN1 CSA = CSB = 00/11 RFA = RFB = 00 g. 4-channel window comparator with internal reference - V AREF+Δ B AIN0 ...
Page 130
... Notes: 1. CONA must be cleared to 0 before changing CSA[1-0]. 2. Debouncing modes require the use of Timer 1 to generate the sampling delay. AT89LP3240/6440 130 CONA CFA CENA (1) Interrupt Mode Negative (Low) level Positive edge (2) Toggle with debouncing ...
Page 131
... AIN1 (P2.5) AIN2 (P2.6) AIN3 (P2.7) CMB0 Interrupt Mode 0 Negative (Low) level 1 Positive edge (2) 0 Toggle with debouncing 1 Positive edge with debouncing 0 Negative edge 1 Toggle 0 Negative edge with debouncing 1 Positive (High) level AT89LP3240/6440 Reset Value = 1100 0000B CENB CMB2 CMB1 (2) (2) CMB0 0 131 ...
Page 132
... RFA0 A- Channel 0 0 AIN1 (P2. Internal Internal Internal V Notes: 1. CONB (ACSRB.5) must be cleared to 0 before changing RFB[1-0]. 2. CONA (ACSRA.5) must be cleared to 0 before changing RFA[1-0]. AT89LP3240/6440 132 RFB1 RFB0 CAC1 (1) (~1.2V) AREF-Δ (~1.3V) AREF (~1.4V) AREF+Δ (2) (~1.2V) AREF-Δ ...
Page 133
... Digital-to-Analog/Analog-to-Digital Converter The AT89LP3240/6440 includes a 10-bit Data Converter (DADC) with the following features: • Digital-to-Analog (DAC) or Analog-to-Digital (ADC) Mode • 10-bit Resolution • 6.5 µs Conversion Time • 8 Multiplexed Single-ended Channels or 4 Differential Channels • Selectable 1.0V±10% Internal Reference Voltage • ...
Page 134
... GND INTERNAL 1.0V REFERENCE ADC7 ADC6 ADC5 ADC4 POS. INPUT MUX ADC3 ADC2 ADC1 ADC0 NEG. INPUT MUX AVDD/2 AT89LP3240/6440 134 Example ADC Conversion Codes Left Adjust Single-Ended Mode ( 4000h 1 7FC0h 511/512 C000h V /2 – 1 8040h V /2 – ...
Page 135
... ADC clock frequency to achieve full resolution. 3706C–MICRO–2/11 minus 1 LSB. REF One Conversion Sample & Hold Initialize Circuitry AT89LP3240/6440 /2. In differential DD Figure 20-2. The conversion requires 13 Next Conversion MSB of Result LSB of Result ...
Page 136
... Figure 20-4. DAC Timing Diagram Cycle Number ADC Clock GO/BSY ADIF DADH DADL The equivalent model for the analog output circuitry is illustrated in put resistance of the DAC must drive the pin capacitance and any external load on the pin. AT89LP3240/6440 136 kΩ ADCn C = ...
Page 137
... TRG bits in DADI. A conversion is started every time the selected timer overflows, allowing for conversions to occur at fixed intervals. The GO/BSY bit will 3706C–MICRO–2/ OUT 100 kΩ V OUT 7-BIT ADC PRESCALER CK INTERNAL ÷ 4 8MHz OSC ACK0 ACK1 ACK2 AT89LP3240/6440 DAn C = PIN 10 pF ADC CLOCK SOURCE Figure 137 ...
Page 138
... Place the CPU in Idle during a conversion. • If any Port 0 pins are used as digital outputs essential that these do not switch while a conversion is in progress. Figure 20-7. Example ADC Power Connections (TQFP Package) AT89LP3240/6440 138 ...
Page 139
... ADC.5 ADC ADC.13 ADC.12 ADC. AT89LP3240/6440 Reset Value = 0000 0000B LADJ ACK2 ACK1 Reset Value = 0000 0000B ADC.3 ADC.2 ADC Reset Value = 0000 0000B ADC.10 ADC ACK0 0 ADC ...
Page 140
... AT89LP3240/6440 140 TRG1 TRG0 DIFF ACS0 P0.0 VDD/2 1 P0.1 VDD/2 0 P0.2 VDD/2 1 P0.3 VDD/2 0 P0.4 VDD/2 1 P0.5 VDD/2 0 P0.6 VDD/2 1 P0.7 VDD/2 0 P0.0 P0.1 1 P0.2 P0.3 0 P0.4 P0.5 1 P0.6 P0.7 0 ...
Page 141
... PS1 The WDT time-out period is dependent on the system clock frequency. ------------------------------------------------------ - Time-out Period = Oscillator Frequency MOV WDTRST, #01Eh MOV WDTRST, #0E1h AT89LP3240/6440 (1) Period PS0 (Clock Cycles) 0 16K 1 32K 0 64K 1 128K 0 256K 1 512K 0 1024K 1 2048K ( ) PS ...
Page 142
... Software Reset A Software Reset of the AT89LP3240/6440 is accomplished by writing the software reset sequence 5AH/A5H to the WDTRST SFR. The WDT does not need to be enabled to generate the software reset. A normal software reset will set the SWRST flag in WDTCON. However any time an incorrect sequence is written to WDTRST (i.e. anything other than 1EH/E1H or 5AH/A5H), a software reset will immediately be generated and both the SWRST and WDTOVF flags will be set ...
Page 143
... The AT89LP3240/6440 is fully binary compatible with the 8051 instruction set. The difference between the AT89LP3240/6440 and the standard 8051 is the number of cycles required to exe- cute an instruction. Instructions in the AT89LP3240/6440 may take clock cycles to complete. The execution times of most instructions may be computed using Table 22-1 ...
Page 144
... ANL A, Rn ANL A, direct ANL A, @Ri ANL A, #data ANL direct, A ANL direct, #data ORL A, Rn ORL A, direct ORL A, @Ri ORL A, #data ORL direct, A ORL direct, #data XRL A, Rn AT89LP3240/6440 144 Instruction Execution Times and Exceptions (Continued Bytes ...
Page 145
... Bytes ( ( ( ( AT89LP3240/6440 66- Clock Cycles 8051 AT89LP Hex Code 12 1 E8-EF 12 ...
Page 146
... JMP @A+DPTR JMP @A+PC CJNE A, direct, rel CJNE A, #data, rel CJNE Rn, #data, rel CJNE @Ri, #data, rel CJNE A, @R0, rel CJNE A, @R1, rel DJNZ Rn, rel DJNZ direct, rel NOP (1)(3) BREAK Notes: AT89LP3240/6440 146 Instruction Execution Times and Exceptions (Continued Bytes ...
Page 147
... Example: If On-Chip Debugging is allowed, the following instruction, BREAK will halt instruction execution prior to the immediately following instruction. If debugging is not allowed, the BREAK is treated as a double NOP. Bytes: 2 Cycles: 2 Encoding: A5 Operation: BREAK (PC) ← (PC 3706C–MICRO–2/ AT89LP3240/6440 147 ...
Page 148
... CLR M Function: Clear MAC Accumulator Description: CLR M clears the 40-bit M register. No flags are affected. Example: The M registercontains 123456789AH. The following instruction, CLR M leaves the M register set to 0000000000H. Bytes: 2 Cycles: 2 Encoding: A5 Operation: JMP (M) ← 0 AT89LP3240/6440 148 ...... ...... ; ACC = @R0. ...... ...... ;ACC > @R0 ...
Page 149
... If the Accumulator equals 04H when starting this sequence, execution jumps to label LABEL2. Because AJMP is a 2-byte instruction, the jump instructions start at every other address. Bytes: 2 Cycles: 3 Encoding: A5 Operation: JMP (PC) ← (A) + (PC 3706C–MICRO–2/ AT89LP3240/6440 performed 149 ...
Page 150
... DB 77H DB 88H DB 99H If the subroutine is called with the Accumulator equal to 01H, it returns with 77H in the Accumulator. Bytes: 2 Cycles: 4 Encoding: A5 Operation: MOVC IF (DPS THEN (A) ← ( (A) + (DPTR1) ) ELSE (A) ← ( (A) + (DPTR0) ) AT89LP3240/6440 150 3706C–MICRO–2/11 ...
Page 151
... Data Pointer: DPH1 hold 56H and DPL1 holds 78H. Bytes: 2 Cycles: 3 Encoding: A5 Operation: MOV IF (DPS THEN (DP1H) ← #data (DP1L) ← #data ELSE (DP0H) ← #data (DP0L) ← #data 3706C–MICRO–2/ immed. data 15-8 15-8 7-0 15-8 7-0 AT89LP3240/6440 0 0 immed. data 7-0 151 ...
Page 152
... Example: DPS = 0, DPTR0 contains 0123H and DPTR1 contains 4567H. The following instruction sequence, MOVX A, @DPTR MOVX @/DPTR, A copies the data from address 0123H to 4567H. Bytes: 2 Cycles: 3 (EDATA) 5 (FDATA or XDATA) Encoding: A5 Operation: MOVX IF (DPS THEN ((DPTR1)) ← (A) ELSE ((DPTR0)) ← (A) AT89LP3240/6440 152 3706C– ...
Page 153
... Table 9-2 on page 42 B4H Table 9-3 on page 43 B8H Table 9-4 on page 43 B5H Table 9-5 on page 43 B7H Table 9-6 on page 44 B6H Table 9-7 on page 44 E5H Section 5.1 on page 24 E4H Section 5.1 on page 24 96H Table 3-3 on page 17 80H Table 10-3 on page 45 BAH Table 10-2 and BBH Table 10-2 and AT89LP3240/6440 Table 10-3 on page 45 Table 10-3 on page 45 153 ...
Page 154
... SADEN SBUF SCON SP SPCR SPDR SPSR SPX T2CCA T2CCC T2CCF T2CCH T2CCL T2CON T2MOD TCON TCONB AT89LP3240/6440 154 Special Function Register Cross Reference 90H Table 10-3 on page 45 C2H Table 10-2 and Table 10-3 on page 45 C3H Table 10-2 and Table 10-3 on page 45 A0H Table 10-3 on page 45 C4H Table 10-2 ...
Page 155
... WDTCON WDTRST 24. On-Chip Debug System The AT89LP3240/6440 On-Chip Debug (OCD) System uses a two-wire serial interface to con- trol program flow; read, modify, and write the system state; and program the nonvolatile memory. The OCD System has the following features: • Complete program flow control • ...
Page 156
... OCD is disabled. 24.3 Limitations of On-Chip Debug The AT89LP3240/6440 is a fully-featured microcontroller that multiplexes several functions on its limited I/O pins. Some device functionality must be sacrificed to provide resources for On- Chip Debugging. The On-Chip Debug System has the following limitations: • The Debug Clock pin (DCL) is physically located on that same pin as Port Pin P4.2 and the External Reset (RST) ...
Page 157
... In-System Programming eliminates the need for physical removal of the chips from the system. This will save time and money, both during development in the lab, and when updating the software or parameters in the field. The programming interface of the AT89LP3240/6440 includes the following features: • ...
Page 158
... Figure 25-2. Parallel Programming Device Connections The Programming Interface is the only means of externally programming the AT89LP3240/6440 microcontroller. The Interface can be used to program the device both in-system and in a stand- alone serial programmer. The Interface does not require any clock other than SCK and is not limited by the system clock frequency ...
Page 159
... The ISP interface uses the SPI clock mode 0 (CPOL = 0, CPHA = 0) exclusively with a maximum frequency of 5 MHz. • The AT89LP3240/6440 will enter programming mode only when its reset line (RST) is active (low). To simplify this operation recommended that the target reset can be controlled by the In-System programmer ...
Page 160
... Page oriented instructions always include a full 16-bit address. The higher order bits select the page and the lower order bits select the byte within that page. The AT89LP3240/6440 allocates 6 bits for byte address, 1 bit for low/high half page selection and 9 bits for page address. The half page to be accessed is always fixed by the page address and half select as transmitted ...
Page 161
... Preamble 2 Opcode Address High X X WRITE 55h Opcode Address High READ 55h Opcode Address High AT89LP3240/6440 Table 25-2 on page 162 Address Low Data Data Out ...
Page 162
... AT89LP6440: 1EH 8. Symbol Key: a: Page Address Bit s: Half Page Select Bit b: Byte Address Bit x: Don’t Care Bit AT89LP3240/6440 162 Opcode Addr High 1010 1100 0101 0011 1010 1100 0011 0101 1000 1010 0110 0000 xxxx xxxx 0101 0001 xxxx xxxx ...
Page 163
... Flash Security The AT89LP3240/6440 provides two Lock Bits for Flash Code and Data Memory security. Lock bits can be left unprogrammed (FFh) or programmed (00h) to obtain the protection levels listed in ...
Page 164
... User Configuration Fuses The AT89LP3240/6440 includes 11 user fuses for configuration of the device. Each fuse is accessed at a separate address in the User Fuse Row as listed in by programming 00h to their locations. Programming FFh to a fuse location will cause that fuse to maintain its previous state. To set a fuse (set to FFh) the fuse row must be erased and then reprogrammed using the Fuse Write with Auto-erase command ...
Page 165
... The second page of the User Signature Array (0080H–00FFH) contains analog configuration parameters for the AT89LP3240/6440. Each byte represents a parameter as listed in and is preset in the factory. The parameters are read at POR and the device is configured accordingly. The second page of the array is not affected by Chip Erase. Other bytes in this page may be used as additional signature space ...
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... MOSI 25.9.3 ISP Start Sequence Execute this sequence to exit CPU execution mode and enter ISP mode when the device has passed Power-On Reset and is already operational. 1. Drive RST low. 2. Drive SS high. 3. Wait t 4. Start programming session. AT89LP3240/6440 166 PWRUP RST SS SCK ...
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... RHZ V DD XTAL1 RST t SS SSZ t SSD SCK MISO MOSI The waveforms on this page are not to scale. Figure 25-11. The SCK phase and polarity follow SPI clock mode 0 (CPOL = 0, AT89LP3240/6440 t RLZ t t STL ZSS t SSE HIGH Z HIGH Z t RHZ HIGH Z HIGH Z 167 ...
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... CPHA = 0) where bits are sampled on the rising edge of SCK and output on the falling edge of SCK. For more detailed timing information see Figure 25-11. ISP Byte Sequence Figure 25-12. Serial Programming Interface Timing SS SCK MISO MOSI Figure 25-13. Parallel Programming Interface Timing SS SCK OE P0 AT89LP3240/6440 168 SCK MOSI MISO Data Sampled t ...
Page 169
... SS Disable Lag Time SSD SCK Setup to SS Low ZSS SCK Hold after SS High SSZ Write Cycle Time WR Write Cycle with Auto-Erase Time Chip Erase Cycle Time ERS independent SCK CLCL AT89LP3240/6440 25-8, Figure 25-9, Figure 25-10, Figure 25-12 Min Max 100 ...
Page 170
... Under steady state (non-transient) conditions, I Maximum I per port pin Maximum total I for all output pins exceeds the test condition than the listed test conditions. 2. Minimum V for Power-down is 2V. DD AT89LP3240/6440 170 *NOTICE: Condition mA 2.7V 85° ± 10 -50 µA, V ...
Page 171
... All current consumption measurements are performed with all I/O pins configured as quasi-bidi- rectional (with internal pull-ups). A square wave generator with rail-to-rail output is used as an external clock source for consumption versus frequency measurements. 3706C–MICRO–2/11 shows the safe operating frequencies for the AT89LP3240/6440 versus supply volt ...
Page 172
... Supply Current (Internal Oscillator) Figure 26-3. Active Supply Current vs. V Figure 26-4. Idle Supply Current vs. V AT89LP3240/6440 172 DD Active Supply Current vs. Vcc 8MHz Internal Oscillator 6.5 6.0 5.5 5.0 4.5 4.0 3.5 2.4 2.7 3.0 Vcc (V) (8MHz Internal Oscillator) DD Idle Supply Current vs. Vcc 8MHz Internal Oscillator 2.00 1.75 1.50 1.25 1.00 2.4 2.7 3.0 Vcc (V) (8MHz Internal Oscillator) 3.3 3.6 3.3 3.6 85C -40C 25C ...
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... Figure 26-6. Idle Supply Current vs. Frequency 3706C–MICRO–2/11 Active Supply Current vs. Frequency External Clock Source Frequency (MHz) Idle Supply Current vs. Frequency External Clock Source Frequency (MHz) AT89LP3240/6440 3.6V 3.3V 3.0V 2.7V 2.4V 3.6V 3.3V 3.0V 2.7V 2.4V 173 ...
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... Quasi-Bidirectional Input Figure 26-7. Quasi-bidirectional Input Transition Current at 3.3V 26.4.4 Quasi-Bidirectional Output Figure 26-8. Quasi-Bidirectional Output I-V Source Characteristic at 3V AT89LP3240/6440 174 0.0 0.4 0.8 1.2 1.6 0 -20 -40 -60 -80 -100 -120 V (V) IL 0.0 0.5 1.0 1.5 0 -20 -40 -60 -80 -100 V OH 2.0 2.4 2.8 3.2 2.0 2.5 3.0 (V) 85C -40C 25C 85C -40C 25C 3706C–MICRO–2/11 ...
Page 175
... Figure 26-10. Push-Pull Output I-V Sink Characteristic at 3V Note: 26.5 Clock Characteristics Figure 26-11. External Clock Drive Waveform 3706C–MICRO–2/11 2.4 2.5 2 -10 V OH1 0.0 0.1 0 The I /V characteristic applies to Push-Pull, Quasi-Bidirectional and Open-Drain modes AT89LP3240/6440 2.7 2.8 2.9 3.0 (V) 0.3 0.4 0.5 (V) 85C -40C 25C 85C -40C 25C 175 ...
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... No wait state (single-cycle) execution speed Table 26-2. Clock Characteristics Symbol Parameter f Crystal Oscillator Frequency XTAL f Internal Oscillator Frequency RC Figure 26-12. Typical Internal Oscillator Frequency vs. VCC 8.10 8.05 8.00 7.95 7.90 7.85 7.80 2.4 AT89LP3240/6440 176 = -40°C to 85°C and V = 2.4 to 3.6V, unless otherwise noted 2.4V to 3.6V DD Min Max Condition Low Speed Oscillator ...
Page 177
... Replacing capacitor C1 with a resistor MΩ results in similar swing levels on XTAL1. Figure 26-14. Typical Crystal Oscillator Swing with Ceramic Resonator and C1=C2, T 4.0 3.5 3.0 2.5 2.0 1.5 1.0 4 3706C–MICRO–2/ Frequency (MHz Frequency (MHz) AT89LP3240/6440 = 25°C A 3.6V 15pF 3.6V 10pF 3.6V 5pF 2.4V 15pF 2.4V 10pF 2.4V 5pF 20 = 25°C A 3.6V 15pF 3.6V 10pF 3.6V 5pF 2.4V 15pF 2.4V 10pF 2.4V 5pF 20 ...
Page 178
... High to ALE High WHLH Notes: 1. This assumes 50% clock duty cycle. The half period depends on the clock high value t 2. This assumes 50% clock duty cycle. The half period depends on the clock low value t AT89LP3240/6440 178 = -40°C to 85°C and V = 2.4 to 3.6V, unless otherwise noted. A ...
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... A8 - A15 FROM DPH OR P2.0 - P2.7 t LHLL t t LLWL WLWH t QVWX t LLAX DATA OUT t QVWH t AVWL A8 - A15 FROM DPH OR P2.0 - P2.7 = -40°C to 85°C and V A AT89LP3240/6440 using wait states. CLCL t WHLH t t RLDV RHDZ t RHDX DATA IN t WHAX P2 t WHLH t WHQX t WHAX ...
Page 180
... Output Enable Time SOE t Output Disable Time SOX t Slave Enable Lead Time SSE t Slave Disable Lag Time SSD Figure 26-17. SPI Master Timing (CPHA = 0) SS SCK (CPOL = 0) SCK (CPOL = 1) MISO MOSI AT89LP3240/6440 180 Min 10 10 Min 41.6 4t CLCL 1 CLCL 1 CLCL ...
Page 181
... Figure 26-20. SPI Slave Timing (CPHA = 1) SS SCK (CPOL = 0) SCK (CPOL = 1) MISO MOSI 3706C–MICRO–2/ SCK SSE t t SHSL SLSH t t SLSH SHSL SOV SOH SOE t SF AT89LP3240/6440 t t SSD SF t SOX t t SIS SIH SOV 181 ...
Page 182
... Two-wire Serial Interface Characteristics Table 26-7 describes the requirements for devices connected to the Two-wire Serial Bus. The AT89LP3240/6440 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions. The values shown in this table are valid for T = -40°C to 85°C and ...
Page 183
... SMOD1 = 0 Min 4t -15 CLCL 3t -15 CLCL t -15 CLCL 0 15 SMOD1 = Valid Valid Valid SMOD1 = Valid Valid Valid AT89LP3240/6440 SU;DAT t SU;STO SMOD1 = 1 Max Min Max 2t -15 CLCL t -15 CLCL t -15 CLCL Valid Valid Valid ...
Page 184
... OS V Analog Reference Voltage AREF V Reference Delta Voltage ΔREF t Comparator Propagation Delay CMP t Reference Settling Time AREF Figure 26-23. Analog Reference Voltage Typical Characteristics 1.5 1.4 1.3 1.2 1.1 2.4 AT89LP3240/6440 184 = -40°C to 85°C and Condition – 20mV 2.4V IN+ IN- DD 2.7 3.0 3.3 Vcc (V) = 2.4 to 3.6V, unless otherwise noted. ...
Page 185
... External Reference V DD Internal Reference GND Condition ≥ ACK CLCL 11t External Reference V DD Internal Reference AT89LP3240/6440 = 2.4 to 3.6V, unless otherwise noted. Min Typical Max 500 14t ACK ACK 2t CLCL / ...
Page 186
... Timers 0, 1 and 2 are configured to be free running in their default timer modes. The CPU exe- cutes a simple random number generator that accesses RAM, the SFR bus and exercises the ALU and hardware multiplier. AT89LP3240/6440 186 1. AC Inputs during testing are driven at V measurements are made at V min. for a logic “ ...
Page 187
... Tests CC in Active and Idle Modes 0. 0.1V CC 0.45V t CHCL Power-down Measurement.All Other Pins are Dis- CC connected 3. RST (NC) XTAL2 XTAL1 GND AT89LP3240/6440 CLCH CHCL t CHCX t CLCH t CHCX t CLCL 187 ...
Page 188
... Wide, Plastic Dual Inline Package (PDIP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 44M1 44-pad 1.0 mm Body, Plastic Very Thin Quad Flat No Lead Package (VQFN/MLF) AT89LP3240/6440 188 Ordering Code AT89LP3240-20AU AT89LP3240-20PU AT89LP3240-20JU AT89LP3240-20MU AT89LP6440-20AU AT89LP6440-20PU AT89LP6440-20JU AT89LP6440-20MU Package Types Package Operation Range 44A 40P6 44J ...
Page 189
... Orchard Parkway San Jose, CA 95131 R 3706C–MICRO–2/11 B PIN 1 IDENTIFIER TITLE 44A, 44-lead Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) AT89LP3240/6440 A2 A COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM SYMBOL A – – A1 0.05 – ...
Page 190
... SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R AT89LP3240/6440 190 D PIN 0º ~ 15º REF ...
Page 191
... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 3706C–MICRO–2/11 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) AT89LP3240/6440 0.318(0.0125) 0.191(0.0075) D2/ COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 4 ...
Page 192
... VQFN/MLF D Marked Pin TOP VIEW BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3. Package Drawing Contact: packagedrawings@atmel.com AT89LP3240/6440 192 E Pin #1 Corner Pin #1 Option A 1 Triangle 2 3 Option B Pin #1 Chamfer (C 0.30) Option C Pin #1 Notch e (0.20 R) TITLE 44M1, 44-pad ...
Page 193
... Removed Preliminary status • Updated “DC Characteristics” on page 170 • Updated “Typical Characteristics” on page 171 • Renamed AVDD to VDD • Added section “System Configuration” on page 8 • Added the AT89LP3240 device • Updated oscillator connection diagram, Figure 6-1 on page 31 193 ...
Page 194
... AT89LP3240/6440 194 3706C–MICRO–2/11 ...
Page 195
... Internal Data Memory ......................................................................................12 3.3 External Data Memory .....................................................................................13 3.4 Extended Stack ...............................................................................................20 3.5 In-Application Programming (IAP) ...................................................................21 5.1 Multiply–Accumulate Unit (MAC) .....................................................................24 5.2 Enhanced Dual Data Pointers .........................................................................25 5.3 Instruction Set Extensions ...............................................................................30 6.1 Crystal Oscillator .............................................................................................31 6.2 External Clock Source .....................................................................................32 6.3 Internal RC Oscillator ......................................................................................32 6.4 System Clock Out ............................................................................................32 6.5 System Clock Divider ......................................................................................32 7.1 Power-on Reset ...............................................................................................33 7.2 Brown-out Reset ..............................................................................................35 7.3 External Reset .................................................................................................35 AT89LP3240/6440 i ...
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... Table of Contents (Continued) 8 Power Saving Modes ............................................................................. 36 9 Interrupts ................................................................................................ 39 10 I/O Ports .................................................................................................. 45 11 Enhanced Timer 0 and Timer 1 with PWM ........................................... 51 12 Enhanced Timer 2 .................................................................................. 60 13 Compare/Capture Array ........................................................................ 69 14 External Interrupts ................................................................................. 82 15 General-purpose Interrupts .................................................................. 83 AT89LP3240/6440 ii 7.4 Watchdog Reset ..............................................................................................36 7.5 Software Reset ................................................................................................36 8.1 Idle Mode .........................................................................................................36 8.2 Power-down Mode ...........................................................................................37 8.3 Reducing Power Consumption ........................................................................38 9 ...
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... Register Overview .........................................................................................112 18.5 Using the TWI ................................................................................................113 18.6 Transmission Modes .....................................................................................115 19.1 Analog Input Muxes .......................................................................................127 19.2 Internal Reference Voltage ............................................................................128 19.3 Comparator Interrupt Debouncing .................................................................128 20.1 ADC Operation ..............................................................................................135 20.2 DAC Operation ..............................................................................................136 20.3 Clock Selection ..............................................................................................137 20.4 Starting a Conversion ....................................................................................137 20.5 Noise Considerations ....................................................................................138 21.1 Software Reset ..............................................................................................142 AT89LP3240/6440 iii ...
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... Table of Contents (Continued) 22 Instruction Set Summary .................................................................... 143 23 Register Index ...................................................................................... 153 24 On-Chip Debug System ....................................................................... 155 25 Programming the Flash Memory ........................................................ 157 26 Electrical Characteristics .................................................................... 170 27 Ordering Information ........................................................................... 188 AT89LP3240/6440 iv 22.1 Instruction Set Extensions .............................................................................147 24.1 Physical Interface ..........................................................................................155 24.2 Software Breakpoints ....................................................................................156 24.3 Limitations of On-Chip Debug .......................................................................156 25.1 Physical Interface ..........................................................................................157 25 ...
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... Table of Contents (Continued) 28 Packaging Information ........................................................................ 189 29 Revision History ................................................................................... 193 Table of Contents....................................................................................... i 3706C–MICRO–2/11 28.1 44A – TQFP ...................................................................................................189 28.2 40P6 – PDIP ..................................................................................................190 28.3 44J – PLCC ...................................................................................................191 28.4 44M1 – VQFN/MLF .......................................................................................192 AT89LP3240/6440 v ...
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... Atmel , Atmel logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’ ...