AT89LP3240 Atmel Corporation, AT89LP3240 Datasheet - Page 89

• Manufacturer Part Number: AT89LP3240
• Manufacturer: Atmel Corporation

Specifications of AT89LP3240

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 38
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 4.25
• Eeprom (bytes): 8192
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 3.6
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

16.3
3706C–MICRO–2/11
More About Mode 0
In Mode 0, the UART is configured as a two wire half-duplex synchronous serial interface. Serial
data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmit-
ted/received, with the LSB first.
the serial port in Mode 0 and associated timing. The baud rate is programmable to 1/2 or 1/4 the
oscillator frequency by setting/clearing the SMOD1 bit. However, changing SMOD1 has an
effect on the relationship between the clock and data as described below. The baud rate can
also be generated by Timer 1 by setting TB8.
Table 16-4.
Transmission is initiated by any instruction that uses SBUF as a destination register. The “write
to SBUF” signal also loads a “1” into the 9th position of the transmit shift register and tells the TX
Control Block to begin a transmission. The internal timing is such that one full bit slot may elapse
between “write to SBUF” and activation of SEND.
SEND transfers the output of the shift register to the alternate output function line of P3.0, and
also transfers Shift Clock to the alternate output function line of P3.1. As data bits shift out to the
right, “0”s come in from the left. When the MSB of the data byte is at the output position of the
shift register, the “1” that was initially loaded into the 9th position is just to the left of the MSB,
and all positions to the left of that contain “0”s. This condition flags the TX Control block to do
one last shift, then deactivate SEND and set TI.
Reception is initiated by the condition REN = 1 and R1 = 0. At the next clock cycle, the RX Con-
trol unit writes the bits 11111110 to the receive shift register and activates RECEIVE in the next
clock phase. RECEIVE enables Shift Clock to the alternate output function line of P3.1. As data
bits come in from the right, “1”s shift out to the left. When the “0” that was initially loaded into the
right-most position arrives at the left-most position in the shift register, it flags the RX Control
block to do one last shift and load SBUF. Then RECEIVE is cleared and RI is set.
The relationship between the shift clock and data is determined by the combination of the SM2
and SMOD1 bits as listed in
idle state of the clock when not currently transmitting/receiving. The SMOD1 bit determines if the
output data is stable for both edges of the clock, or just one.
Table 16-5.
SM2
TB8
0
0
1
1
0
0
1
1
SMOD1
SMOD1
Mode 0 Baud Rates
0
1
0
1
Mode 0 Clock and Data Modes
0
1
0
1
Clock Idle
(Timer 1 Overflow) / 4
(Timer 1 Overflow) / 2
High
High
Low
Low
Table 16-5
Figure 16-1 on page 90
Baud Rate
f
f
SYS
SYS
/4
/2
and shown in
Negative edge of clock
Negative edge of clock
While clock is high
While clock is low
Table 16-4
Data Changed
Figure
shows a simplified functional diagram of
lists the baud rate options for Mode 0.
AT89LP3240/6440
16-2. The SM2 bit determines the
Negative edge of clock
Positive edge of clock
Positive edge of clock
Positive edge of clock
Data Sampled
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