AT89LP6440 Atmel Corporation, AT89LP6440 Datasheet - Page 74

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AT89LP6440

Manufacturer Part Number
AT89LP6440
Description
Manufacturer
Atmel Corporation
Datasheet

Specifications of AT89LP6440

Flash (kbytes)
64 Kbytes
Max. Operating Frequency
20 MHz
Cpu
8051-1C
Max I/o Pins
38
Spi
1
Twi (i2c)
1
Uart
1
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
153.8
Sram (kbytes)
4.25
Eeprom (bytes)
8192
Self Program Memory
IAP
Operating Voltage (vcc)
2.4 to 3.6
Timers
3
Isp
SPI/OCD
Watchdog
Yes

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Table 13-5.
Notes:
74
T2CCC Address = 0D4H
Not Bit Addressable
Bit
Symbol
CIENx
CDIRx
CTCx
CCMx
CxM[2-0]
1. All writes/reads to/from T2CCC will access channel X as currently selected by T2CCA.The control registers for the remain-
2. Analog Comparator A events are determined by the CMA
3. Analog Comparator B events are determined by the CMB
4. Asymmetrical versus Symmetrical PWM is determined by the Timer 2 Count Mode. See
AT89LP3240/6440
CIENx
ing unselected channels are not accessible.
7
Function
Channel X Interrupt Enable. When set, channel X’s interrupt flag, CCFx in T2CCF, will generate an interrupt when ECC
= 1. Clear to disable interrupts from channel X.
Channel X Capture Direction. In dual-slope modes, a compare/capture event on channel X will store the current count
direction into CDIRx. Up-counting = 0 and down-counting = 1. Modifying this bit has no effect.
Clear Timer on Compare/Capture of Channel X. When set, the Timer 2 registers TL2 and TH2 will be cleared by a
compare/capture event on channel X. When cleared, Timer 2 is unaffected by channel X events.
Channel X Compare/Capture Mode. When CCMx = 1, channel X operates in compare mode. When CCMx = 0, channel
X operates in capture mode.
Channel X Mode. Selects the output/input events for compare/capture channel X.
CxM2
0
0
0
0
1
1
1
1
CxM2
0
0
0
0
1
1
1
1
T2CCC – Timer/Counter 2 Compare/Capture Control
CxM1
0
0
1
1
0
0
1
1
CxM1
0
0
1
1
0
0
1
1
CDIRx
6
CxM0
0
1
0
1
0
1
0
1
CxM0
0
1
0
1
0
1
0
1
5
Capture Event (CCMx = 0)
Disabled
Trigger on negative edge of CCx pin
Trigger on positive edge of CCx pin
Trigger on either edge of CCx pin
Trigger on Timer 0 overflow
Trigger on Timer 1 overflow
Trigger on Analog Comparator A Event
Trigger on Analog Comparator B Event
Compare Action (CCMx = 1)
Output disabled (interrupt only)
Set CCx pin on compare match
Clear CCx pin on compare match
Toggle CCx pin on compare match
Inverting Pulse Width Modulation
Non-Inverting Pulse Width Modulation
Reserved
Reserved
CTCx
4
2-0
2-0
CCMx
bits in ACSRA. See
bits in ACSRB. See
3
(4)
(4)
CxM2
(2)
(3)
2
Table 19-1 on page
Table 19-2 on page
Reset Value = 00X0 0000B
Section 13.4 on page
CxM1
1
131.
130.
CxM0
3706C–MICRO–2/11
0
77.

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