AT90CAN64 Atmel Corporation, AT90CAN64 Datasheet - Page 180

• Manufacturer Part Number: AT90CAN64
• Manufacturer: Atmel Corporation

Specifications of AT90CAN64

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Can: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

17.4.2
17.4.3
180
AT90CAN32/64/128
Double Speed Operation (U2X)
External Clock
units use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the
UMSELn, U2Xn and DDR_XCKn bits.
Table 17-1
ing the UBRRn value for each mode of operation using an internally generated clock source.
Table 17-1.
Note:
Some examples of UBRRn values for some system clock frequencies are found in
(see
The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has
effect for the asynchronous operation. Set this bit to zero when using synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling
the transfer rate for asynchronous communication. Note however that the Receiver will in this
case only use half the number of samples (reduced from 16 to 8) for data sampling and clock
recovery, and therefore a more accurate baud rate setting and system clock are required when
this mode is used. For the Transmitter, there are no downsides.
External clocking is used by the synchronous slave modes of operation. The description in this
section refers to
External clock input from the XCKn pin is sampled by a synchronization register to minimize the
chance of meta-stability. The output from the synchronization register must then pass through
an edge detector before it can be used by the Transmitter and Receiver. This process intro-
duces a two CPU clock period delay and therefore the maximum external XCKn clock frequency
is limited by the following equation:
Operating Mode
Asynchronous Normal mode
(U2Xn = 0)
Asynchronous Double Speed
mode (U2Xn = 1)
Synchronous Master mode
page
1. The baud rate is defined to be the transfer rate in bit per second (bps)
200).
contains equations for calculating the baud rate (in bits per second) and for calculat-
BAUD
f
UBRRn
Equations for Calculating Baud Rate Register Setting
clk
Figure 17-2
io
for details.
Baud rate (in bits per second, bps).
System I/O Clock frequency.
Contents of the UBRRnH and UBRRnL Registers, (0-4095).
Equation for Calculating Baud
BAUD
BAUD
BAUD
=
=
=
Rate
----------------------------------------- -
16 UBRRn
-------------------------------------- -
8 UBRRn
-------------------------------------- -
2 UBRRn
f
XCKn
(
(
(
(1)
f
f
f
CLKio
CLKio
CLKio
<
f
--------------- -
CLKio
4
+
+
+
1
1
1
)
)
)
UBRRn
Equation for Calculating
UBRRn
UBRRn
UBRRn Value
=
=
=
----------------------- - 1
16BAUD
------------------- - 1
8BAUD
------------------- - 1
2BAUD
f
f
f
CLKio
CLKio
CLKio
7679H–CAN–08/08
Table 17-9
–
–
–