AT90CAN64 Atmel Corporation, AT90CAN64 Datasheet - Page 97

• Manufacturer Part Number: AT90CAN64
• Manufacturer: Atmel Corporation

Specifications of AT90CAN64

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Can: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7679H–CAN–08/08
T3
T1
T0
Figure 11-1. T3/T1/T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the T3/T1/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T3/T1/T0 has been stable for at
least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is
generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
An external clock source can not be prescaled.
Figure 11-2. Prescaler for Timer/Counter3, Timer/Counter1 and Timer/Counter0
Note:
Synchronization
Synchronization
Synchronization
CS00
CS01
CS02
1. The synchronization logic on the input pins (
Tn
clk
I/O
TIMER/COUNTER0 CLOCK SOURCE
0
PSR310
CK
D
LE
ExtClk
clk
T0
Q
< f
clk_I/O
Synchronization
D
/2) given a 50/50 % duty cycle. Since the edge detector uses
Q
CS10
CS11
CS12
Clear
TIMER/COUNTER1 CLOCK SOURCE
0
T0/T1/T3)
10-BIT T/C PRESCALER
clk
T1
AT90CAN32/64/128
is shown in
D
CS30
CS31
CS32
Q
Figure
Edge Detector
TIMER/COUNTER3 CLOCK SOURCE
0
11-1.
clk_I/O
(1)
clk
T3
/2.5.
Tn_sync
(To Clock
Select Logic)
97