AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet
AT90PWM81
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AT90PWM81 Summary of contents
Page 1
... One 10-bit DAC – Three Analog Comparator with • Resistor-Array to adjust comparison voltage • DAC to adjust comparison voltage – One SPI – 3 External interrupts – Programmable Watchdog Timer with Separate On-Chip Oscillator 8-bit Microcontroller with 8K Bytes In- System Programmable Flash AT90PWM81 7734P–AVR–08/10 ...
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... Flash size EEPROM size RAM size PSC 12 bits with extended features PSC 12 bits Timer 8 bits Timer 16 bits ADC inputs Amplifiers for ADC Temperature sensor Analog Comparators DAC DAC amplifiers UART/DALI SPI AT90PWM81 2 PWM81 configurations SO20 QFN32 512 512 256 256 1 1 ...
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... Pin Configurations Figure 2-1. 7734P–AVR–08/10 20 Pin Packages AT90PWM81 3 ...
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... Figure 2-2. (ACMP3_OUT_A/SS/CLKO) PD0 (ACPM1_OUT/PSCIN2/XTAL1) PE1 AT90PWM81 4 32-Pin Packages AT90PWM81 QFN 32 5 (PSCOUT20) PB1 3 (INT0/PSCOUT21) PB2 4 VCC 5 GND PD5 (AMP0-/ADC7) 22 PE3/AREF/ADC6 21 AGND 20 AVCC PB5 (ADC5/INT1/SCK/ACMP2) 19 PD4 (PSCIN2A/ACMP3M/ADC4 7734P–AVR–08/10 ...
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... PSCx Digital Input PSC reduced output n PSC reduced Digital Input Analog Comparator n Positive Input Analog Comparator n Negative Input Negative input for analog comparators Analog Comparator n Output Analog Differential Amplifier n Input Channel Analog Differential Amplifier n Input Channel Analog Converter Input Channel n AT90PWM81 5 ...
Page 6
... As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the AT90PWM81 as listed on Table 9-3 on page AT90PWM81 ...
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... As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the AT90PWM81 as listed on Table 9-6 on page 76 2.1.5 Port E (P32 ...
Page 8
... Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the pro- gram memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. AT90PWM81 8 Block Diagram of the AVR Architecture Program ...
Page 9
... The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the AT90PWM81 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...
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... The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Descrip- tion” for detailed information. AT90PWM81 ...
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... R30 R31 Figure 3-2, each register is also assigned a data memory address, mapping them directly into Figure 3-3. The X-, Y-, and Z-registers R27 (0x1B AT90PWM81 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A X-register Low Byte 0x1B X-register High Byte ...
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... Figure 3-4 tecture and the fast-access Register File concept. This is the basic pipelining concept to obtain MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. AT90PWM81 12 7 R29 (0x1D) 15 ...
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... Register Operands Fetch ALU Operation Execute Result Write Back “Memory Programming” on page 247 “Interrupts” on page “Interrupts” on page 61 for more information. The Reset Vector can also be moved to the start of 232. AT90PWM81 for details. 61. The list also determines the priority “ ...
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... Assembly Code Example sei sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) AT90PWM81 14 ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) /* store SREG value */ /* restore SREG value (I-bit) */ ...
Page 15
... This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 7734P–AVR–08/10 AT90PWM81 15 ...
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... Memories This section describes the different memories in the AT90PWM81. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the AT90PWM81 fea- tures an EEPROM Memory for data storage. All three memory spaces are linear and regular. ...
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... When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 256 bytes of internal data SRAM in the AT90PWM81 are all accessible through all these addressing modes. The Register File is described in Figure 4-2. ...
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... EEPROM Data Memory The AT90PWM81 contains 512 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specify- ing the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
Page 19
... Read/Write Initial Value • Bits 15..9 – Reserved Bits These bits are reserved bits in the AT90PWM81 and will always read as zero. • Bits 8..0 – EEAR8..0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 512 bytes EEPROM space ...
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... Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See ming” on page 232 AT90PWM81 20 EEPROM Mode Bits Programming ...
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... EEPAGE bit will be cleared. Loading data into the temporary EEPROM buffer takes three CPU clock cycles. If EEDR is written while EEPAGE is set, the CPU is halted to ensure that the operation takes three cycles. 7734P–AVR–08/10 EEPROM Programming Time. Number of Calibrated RC Oscillator Cycles 26368 AT90PWM81 Table 4-2 lists the typical programming Typ Programming Time 3 ...
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... EEPE (within four cycles after EEMPE has been written). 4.4 Fuse Bits The AT90PWM81 has three Fuse bytes. fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed. ...
Page 23
... The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz. See 28 for details. 3. The CKOUT Fuse allows the system clock to be output on PORTD0. See page 34 for details. 4. See “System Clock Prescaler” on page 38 AT90PWM81 Default Value 1 (unprogrammed) 1 (unprogrammed) 0 (programmed, SPI programming enabled) 1 (unprogrammed) 1 (unprogrammed), EEPROM ...
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... EEPROM_write (unsigned int uiAddress, unsigned char ucData Wait for completion of previous write */ while(EECR & (1<<EEWE)) /* Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); } AT90PWM81 24 ; 7734P–AVR–08/10 ...
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... Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from data register */ return EEDR; the EEPROM data can be corrupted because the supply voltage is too low for CC, AT90PWM81 reset Protection circuit can be used reset occurs CC 25 ...
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... I/O Memory The I/O space definition of the AT90PWM81 is shown in All AT90PWM81 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose work- ing registers and the I/O space. I/O registers within the address range 0x00 - 0x1F are directly bit- accessible using the SBI and CBI instructions ...
Page 27
... System Clock and Clock Options The AT90PWM81 provides a large number of clock sources. Those can be divided in two categories: internal and external. After reset, CKSEL Fuses select one clock source. Once the device is running, software clock switching is available on any other clock sources. Some hardware controls are provided for clock switching management but some specific procedures must be observed ...
Page 28
... PLL output divided by 4/ PLL driven by External clock Calibrated Internal RC Oscillator 1MHz External Crystal/Ceramic Resonator (3.0 - 8.0 MHz) External Crystal/Ceramic Resonator (0.9 - 3.0 MHz) External Crystal/Ceramic Resonator (0.9 - 3.0 MHz) External Crystal/Ceramic Resonator (3.0 - 8.0 MHz) External Crystal/Ceramic Resonator (3.0 - 8.0 MHz) AT90PWM81 28 (1) , PLL source and PE1 and PE2 functionality System (2) Clock ...
Page 29
... CLKSELR register bits. 5. Ext Osc : External Osc 6. RC Osc : Internal RC Oscillator (1 MHz or 8 MHz Internal Watch Dog RC Oscillator 128 kHz 8. Ext Clk : External Clock Input Number of Watchdog Oscillator Cycles Typ. Time-out AT90PWM81 (3) CKSEL3..0 (2) (4) CSEL3..0 PE1 1100 XTAL1 ...
Page 30
... When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in page 30. Table 5-4. Power Conditions BOD enabled Fast rising power Slowly rising power Note: AT90PWM81 30 for more details.The RC oscillator can be accessed by two CKSEL or Table 5-1. If selected, it will operate with no external components. During reset, hard- 252. Internal Calibrated RC Oscillator Operating Modes (2) Frequency Range (MHz) 7 ...
Page 31
... Flash Fuse bits 2. CLKSELR register bits Crystal Oscillator Connections C2 C1 AT90PWM81 Additional Delay from Reset Recommended Usage 14CK BOD enabled 14CK + 4 ms Fast rising power 14CK + 64 ms Slowly rising power Reserved Figure 5-2. Either a quartz crystal or a ceramic resonator ...
Page 32
... The CKSEL0 Fuse together with the SUT1..0 Fuses or CSEL0 together with CSUT1..0 field select the start-up times as shown in Table 5-7. CKSEL0 CSEL0 Notes: AT90PWM81 32 Crystal Oscillator Operating Modes (1) Frequency Range (MHz) (2) (3) 0.4 - 0.9 0.9 - 3.0 3.0 - 8.0 8.0 - 16.0 1. Flash Fuse bits. 2. CLKSELR register bits. 3. This option should not be used with crystals, only with ceramic resonators. ...
Page 33
... This clock is generated by a PLL. To keep all PWM accuracy, the frequency factor of PLL must be con- figured by software.. The internal PLL in AT90PWM81 generates a clock frequency multiplied from nominally 8 MHz input. The source of the 8 MHz PLL input clock can be selected from three possible sources (See the on page • ...
Page 34
... Note that the clock will not be output during reset and the normal operation of I/O pin will be overridden when the fuses are programmed. Any clock source can be selected when the clock is output on CLKO. If the System Clock Prescaler is used the divided system clock that is output. AT90PWM81 34 Additional Delay from Reset (V ...
Page 35
... Dynamic Clock Switch 5.3.1 Features AT90PWM81 provides a powerful dynamic clock switch that allows users to turn on and off clocks of the device on the fly. The built-in de-glitching circuitry allows clocks to be enabled or disabled asynchro- nously. This enables efficient power management schemes to be implemented easily and quickly safety application, the dynamic clock switch circuit may continuously monitor the external clock fails ...
Page 36
... External Crystal/Ceramic Resonator 5. PLL output divided by four. The clock switching is performed in a sequence of commands. First, the user (code) must make sure that the new clock source is running. Then the switching command can be entered. At the end, the user (code) AT90PWM81 36 7734P–AVR–08/10 ...
Page 37
... Warning: In the AT90PWM81, only one among the external clock sources can be enabled at a given time and it is not possible to switch from external clock to external oscillator as both sources share one pin. Also not possible to switch the synchronization source of the PLL when the sytem clock is PLL/4. ...
Page 38
... Features The AT90PWM81 system clock can be divided by setting the Clock Prescaler Register – CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...
Page 39
... CLKPCE bit. • Bits 6:4 – Res: Reserved Bits These bits are reserved bits in the AT90PWM81 and will always read as zero. • Bits 3:0 – CLKPS3:0: Clock Prescaler Select Bits These bits define the division factor between the selected clock source and the internal system clock ...
Page 40
... PLL Control and Status Register – PLLCSR Bit $29 ($29) Read/Write Initial Value • Bit 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90PWM81 and always read as zero. • Bit 5..2-– PLLF: PLL Factor The PLLF bits is used to select the multiplication factor of the PLL . Table 5-11. PLLF3..0 ...
Page 41
... CLKCCE bit. • Bits 6:5 – Res: Reserved Bits These bits are reserved bits in the AT90PWM81 and will always read as zero. • Bits 4 – CLKRDY: Clock Ready Flag This flag is the output of the ‘Clock Availability’ logic. ...
Page 42
... Read/Write Initial Value • Bit 7– Res: Reserved Bit This bit is reserved bit in the AT90PWM81 and will always read as zero. • Bit 6 – COUT: Clock Out The COUT bit is initialized with CKOUT Fuse bit. The COUT bit is only used in case of ‘CKOUT’ command. Refer to on page 34 In case of ‘ ...
Page 43
... In case of ‘Recover System Clock Source’ command, CSEL field receives the code of the clock source used to drive the Clock Control Unit as described in 7734P–AVR–08/10 Section 5.2 ”Clock Sources” on page 28 AT90PWM81 Table 5-1 on page 28 for clock source codes. Figure 5-1 on page 27. ...
Page 44
... Timer Overflow interrupts. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by clearing the ACnEN bit in the Analog Comparator Control and Sta- AT90PWM81 44 presents the different clock systems in the AT90PWM81, and their distribution. Active Clock Domains and Wake-up Sources in the Different Sleep Modes. Active Clock Domains X ...
Page 45
... There are several issues to consider when trying to minimize the power consumption in an AVR con- trolled system. In general, sleep modes should be used as much as possible, and the sleep mode should be 7734P–AVR–08/10 , clk , and clk , while allowing the other clocks to run. I/O CPU FLASH “Clock Sources” on page 28. AT90PWM81 “External Interrupts” on page 82 for details. 45 ...
Page 46
... Refer to the section details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to V AT90PWM81 46 “Analog Comparator” on page 194 “Brown-out Detection” on page 52 “ ...
Page 47
... Standby mode is only recommended for use with external crystals or resonators PRPSC2 - PRPSCR PRTIM1 R/W R R/W R AT90PWM81 – SM2 SM1 SM0 R R/W R/W R Table 6-2. Sleep Mode Idle ADC Noise Reduction Power-down Reserved Reserved Reserved ...
Page 48
... Writing a logic one to this bit reduces the consumption of the ADC by stopping the clock to this module. The ADC must be disabled before using this function. The analog comparator cannot use the ADC input MUX when the clock of ADC is stopped. AT90PWM81 48 7734P–AVR–08/10 ...
Page 49
... SUT and CKSEL Fuses. The different selections for the delay period are presented in 7.1.2 Reset Sources The AT90PWM81 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V POT • ...
Page 50
... Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V below the detection level. AT90PWM81 50 Reset Logic Power-on Reset Circuit ...
Page 51
... TIME-OUT INTERNAL RESET MCU Start-up, RESET Extended Externally V POT V CC RESET TIME-OUT INTERNAL RESET Table 7-1) will generate a reset, even if the clock is not running. Shorter pulses are not External Reset During Operation CC AT90PWM81 CC V RST t TOUT – has expired. TOUT – on RST 51 ...
Page 52
... Brown-out Detection AT90PWM81 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hys- ...
Page 53
... Brown-out Reset During Operation BOT- RESET TIME-OUT INTERNAL RESET Watchdog Reset During Operation – – – – AT90PWM81 V BOT+ t TOUT . Refer to page 55 TOUT WDRF BORF EXTRF PORF R/W R/W R/W R/W See Bit Description for details MCUSR 53 ...
Page 54
... Internal Voltage Reference AT90PWM81 features an internal bandgap reference. This bandgap reference is used for Brown-out Detection and can be used as analog input for the analog comparators or the ADC. The internal voltage reference for the DAC and/or the ADC and the comparators is derived from this bandgap voltage. see The Vref voltage is configured thanks to the REFS1 and REFS0 bits in the ADMUX register ...
Page 55
... Note: 7.4 Watchdog Timer AT90PWM81 has an Enhanced Watchdog Timer (WDT). The main features are: • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 1ms to 8s • ...
Page 56
... The following code example shows one assembly and one C function for turning off the Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no inter- rupts will occur during the execution of these functions. Assembly Code Example AT90PWM81 56 (1) 7734P–AVR–08/10 ...
Page 57
... Clear WDRF in MCUSR */ MCUSR &= ~(1<<WDRF); /* Write logical one to WDCE and WDE */ /* Keep old prescaler setting to prevent unintentional time-out */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; __enable_interrupt(); 1. The example code assumes that the part specific header file is included. AT90PWM81 57 ...
Page 58
... This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed. AT90PWM81 58 (1) r16, (1<<WDCE) | (1<<WDE) Got four cycles to set the new values from here - r16, (1< ...
Page 59
... System Reset Mode Interrupt and System Reset 1 1 Mode x x System Reset Mode 1. For the WDTON Fuse “1” means unprogrammed while “0” means programmed. AT90PWM81 Action on Time-out None Interrupt Reset Interrupt, then go to System Reset Mode Reset Table 7-6 on page 60 ...
Page 60
... Table 7-6. WDP3 AT90PWM81 60 Watchdog Timer Prescaler Select Number of WDT Oscillator WDP2 WDP1 WDP0 16K (16384) cycles 32K (32768) cycles 64K (65536) cycles 128K (131072) cycles ...
Page 61
... Interrupts This section describes the specifics of the interrupt handling as performed in AT90PWM81. For a general explanation of the AVR interrupt handling, refer to 8.1 Interrupt Vectors in AT90PWM81 Table 8-1. Vector No Notes: Table 8-2 IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and 7734P– ...
Page 62
... AT90PWM81 62 Reset and Interrupt Vectors Placement in AT90PWM81 IVSEL Reset Address 0 0x000 1 0x000 0 Boot Reset Address 1 Boot Reset Address 1. The Boot Reset Address is shown in Table 20-7 on page unprogrammed while “0” means programmed. ...
Page 63
... When the BOOTRST Fuse is programmed and the Boot section size set to 2K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses in AT90PWM81 is: Address Labels Code .org 0x001 0x001 0x002 ... ...
Page 64
... The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hard- ware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below. AT90PWM81 64 rjmp ...
Page 65
... Move_interrupts(void 7734P–AVR–08/10 ; Enable change of Interrupt Vectors ldi r16, (1<<IVCE) out MCUCR, r16 ; Move interrupts to Boot Flash section ldi r16, (1<<IVSEL) out MCUCR, r16 ret /* Enable change of Interrupt Vectors */ MCUCR = (1<<IVCE); /* Move interrupts to Boot Flash section */ MCUCR = (1<<IVSEL); AT90PWM81 65 ...
Page 66
... Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. AT90PWM81 66 and Ground as indicated in Figure ...
Page 67
... SLEEP: SLEEP CONTROL clk : I/O CLOCK I/O 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk PUD are common to all ports. 80, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at AT90PWM81 Figure 9-2 shows a functional Q D DDxn Q ...
Page 68
... This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. externally applied pin value. The maximum and minimum propagation delays are denoted t t respectively. pd,min AT90PWM81 68 summarizes the control signals for the pin value. Port Pin Configurations PUD PORTxn ...
Page 69
... Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK r16 INSTRUCTIONS out PORTx, r16 SYNC LATCH PINxn r17 AT90PWM81 XXX in r17, PINx 0x00 t pd, max t pd, min 0xFF nop in r17, PINx ...
Page 70
... Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change. AT90PWM81 70 (1) r16, (1< ...
Page 71
... WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk PUD are common to all ports. All other signals are unique for each pin. summarizes the function of the overriding signals. The pin and port indexes from AT90PWM81 Figure 9-5 can be overridden by alternate functions. The over- ...
Page 72
... Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). Se AT90PWM81 72 Generic Description of Overriding Signals for Alternate Functions Full Name ...
Page 73
... MOSI (SPI Master Out Slave In) ADC3 (Analog Input Channel 3) ACMPM reference for analog comparators PSCOUTR1 Output . ADC2 (Analog Input Channel 2) ACMP2M (Analog Comparator 2 Negative Input) INT0 (External Interrupt 0 Input) PSCOUT21 OutpuT PSCOUT20 output T1counter source. PSCOUT23 Output ACMP3_OUT( Analog Comparator3 Output) AT90PWM81 Table 9- ...
Page 74
... INT0, External Interrupt source 0. This pin can serve as an external interrupt source to the MCU. PSCOUT21: Output 1 of PSC 2. • PSCOUT20 – Bit 1 PSCOUT20: Output 0 of PSC 2. • T1/PSCOUT23/ACMP3_OUT – Bit 0 T1, Timer/Counter1 counter source. PSCOUT23: Output 3 of PSC 2. ACMP3_OUT, Analog Comparator3 Output. AT90PWM81 7734P–AVR–08/10 ...
Page 75
... Port B to the overriding signals shown in 71. Overriding Signals for Alternate Functions in PB7..PB4 PB7/PSCOUT22/ PB6/MISO/ ICP1/ADC9 ACMP3/ADC8 Overriding Signals for Alternate Functions in PB3..PB0 PB3/PSCOUTR1/ PB2/PSCOUTR1/ ADC2/ACMP2M ADC2/ACMP2M AT90PWM81 Figure PB5/ADC5/ PB4/MOSI/ADC ACMP2/INT1/SCK 3/ACMPM PB1/ PB0/T1/PSCOUT2 3/ACMP3_OUT PSCOUT20 75 ...
Page 76
... ACMP3M, Analog Comparator 3 Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. ADC4, Analog to Digital Converter, input channel 4. PCSIN2A, PSC 2 Alternate Digital Input. AT90PWM81 76 Port D Pins Alternate Functions Alternate Function ADC10 (Analog Input Channel 10) ...
Page 77
... PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 7734P–AVR–08/10 and Table 9-8 relates the alternate functions of Port D to the overriding signals shown in 71. Overriding Signals for Alternate Functions PD7..PD4 PD7/ ADC10/ PSCINrA PD6/APM0+ AT90PWM81 . PD5/AMP0- PD4/ACMP3M/ /ADC7 ADC2/PSCIN2A Figure 77 ...
Page 78
... This pin can only be used as a digital output pin. It cannot be read as a digital input. • XTAL2/ACMP1M/PSCINr – Bit 2 XTAL2: Chip clock Oscillator pin 2. Used as clock pin for crystal Oscillator or Low-frequency crystal Oscillator. When used as a clock pin, the pin can not be used as an I/O pin. AT90PWM81 78 Overriding Signals for Alternate Functions in PD3..PD0 PD3/ADC1/ ...
Page 79
... Table 9-10. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 7734P–AVR–08/10 relates the alternate functions of Port E to the overriding signals shown in Overriding Signals for Alternate Functions in PE2..PE0 PE2/XTAL2/ACM PE1/XTAL1/PSCI P1M/PSCINr N2/ ACMP1_OUT AT90PWM81 Figure 9-5 on page PE0/RESET/OCD/ INT2 79 ...
Page 80
... Bit Read/Write Initial Value 9.4.5 Port D Data Direction Register – DDRD Bit Read/Write Initial Value 9.4.6 Port D Input Pins Address – PIND Bit Read/Write Initial Value 9.4.7 Port E Data Register – PORTE Bit Read/Write Initial Value AT90PWM81 PORTB7 PORTB6 PORTB5 PORTB4 R/W R/W R/W R ...
Page 81
... Initial Value 7734P–AVR–08/ – – – – – – – – AT90PWM81 – DDE2 DDE1 DDE0 R R/W R/W R – PINE2 PINE1 PINE0 R R/W R/W R/W 0 N/A N/A N/A DDRE ...
Page 82
... If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. Table 10-1. ISCn1 Note: AT90PWM81 82 “Clock Systems and their Distribution” on page “Electrical Characteristics(1)” on page “System Clock and Clock Options” on page ...
Page 83
... These flags are always cleared when INT2:0 are con- figured as level interrupt. 7734P–AVR–08/ R/W R/W R/W R R/W R/W R/W R AT90PWM81 INT2 INT1 IINT0 R/W R/W R/W R INTF2 INTF1 IINTF0 R/W R/W R/W R EIMSK EIFR ...
Page 84
... I/O pins, refer to I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the Timer/Counter Register Description” on page The PRTIM1 bit in Timer/Counter1 module. AT90PWM81 84 “Pin out description” on page 6. CPU accessible I/O Registers, including I/O bits and 96. “Power Reduction Register” on page 45 Figure 11-1 ...
Page 85
... Timer/Counter Block Diagram Count Clear Control Logic Timer/Counter TCNTn ICRn Table 2-1 on page 5 1. Refer to for Timer/Counter1 pin placement and description. 86. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit AT90PWM81 (1) TOVn (Int.Req.) Clock Select clk Tn Edge Detector TOP BOTTOM (Ckio ) ...
Page 86
... The following code examples show how to access the 16-bit Timer Registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit access. AT90PWM81 86 The counter reaches the BOTTOM when it becomes 0x0000. ...
Page 87
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. (1) AT90PWM81 87 ...
Page 88
... Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair. AT90PWM81 88 (1) 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” ...
Page 89
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. AT90PWM81 89 ...
Page 90
... Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. 11-3 shows a block diagram of the counter and its surroundings. Figure 11-3. AT90PWM81 90 ). The latch is transparent in the high period of the internal clk I/O /clk pulse for each positive (CSn2 negative (CSn2 ...
Page 91
... Timer/Counter clock Signalize that TCNT1 has reached maximum value. Signalize that TCNT1 has reached minimum value (zero). ). The clk can be generated from an external or internal clock source, selected by the AT90PWM81 is present or not. A CPU T 1 Figure 11-4. The elements of the block 91 ...
Page 92
... Comparator is selected as trigger source by setting the Analog Comparator Input Capture (AC1ICE) bit in the Analog Comparator Extended Control Register (AC1ECON). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change. AT90PWM81 92 Input Capture Unit Block Diagram ...
Page 93
... Timer/Counter Overflow Flag (TOV1) will be set in the same timer clock cycle as the TCNT1 becomes zero. The TOV1 Flag in this case behaves like a 17th bit, except that it is only set, 7734P–AVR–08/10 (SeeFigure 11-2 on page 90). The edge detector is also identical. “Timer/Counter Timing Diagrams” on page AT90PWM81 94. 93 ...
Page 94
... Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clk enable signal in the following figures. The figures include information on when Interrupt Flags are set. Figure 11-6 AT90PWM81 94 CTC Mode, Timing Diagram shows the count sequence close to TOP in various modes. ...
Page 95
... TCNTn Figure 11-7 Figure 11-7. (clk TCNTn 7734P–AVR–08/10 Timer/Counter Timing Diagram, no Prescaling clk I/O clk Tn (clk /1) I/O TOP - 1 ICFn shows the count sequence close to MAX in various modes.. Timer/Counter Timing Diagram, no Prescaling clk I/O clk Tn /1) I/O MAX-1 TOVn AT90PWM81 TOP BOTTOM BOTTOM + 1 BOTTOM BOTTOM + 1 MAX 95 ...
Page 96
... See the table below for the modes definition Table 11-1. Mode 0 12 • Bit 3 – Reserved • Bit 2:0 – CS12:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 11-2. Table 11-2. CS12 AT90PWM81 ICNC1 ICES1 - WGM13 R/W R/W R R/W ...
Page 97
... See “Accessing 16-bit Registers” on page 86 ICR1[15:8] ICR1[7:0] R/W R/W R/W R – – ICIE1 – R AT90PWM81 R/W R/W R/W R R/W R/W R/W R See “Accessing 16-bit – – – TOIE1 R ...
Page 98
... Initial Value • Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the AT90PWM81, and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13 used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value ...
Page 99
... Power Stage Controller – (PSCn) The Power Stage Controller is a high performance waveform controller. The AT90PWM81 includes one PSC2 block. 12.1 Features • PWM waveform generation function (2 complementary programmable outputs) • Dead time control • Standard mode bit resolution • Frequency and pulse width Resolution Enhancement Mode ( bits) • ...
Page 100
... The PSC is seen as two symmetrical entities. One part named part A which generates the output PSCOUTn0 and the second one named part B which generates the PSCOUTn1 output. Each part has its own PSC Input Module to manage selected input. AT90PWM81 100 Power Stage Controller Block Diagram ...
Page 101
... OCRnSB Part A PSC Input = Module A OCRnRA Waveform = Generator A OCRnSA Part B PICRn PCNFEn PCNFn PFRCnB PCTLn PFRCnA (See “Output Matrix” on page AT90PWM81 PSCOUTn3 POS23 PSCOUTn1 PSCn Input B Output Matrix PSCn Input A PSCOUTn2 POS22 PSCOUTn0 PASDLYn POM2(PSC2 only) PSOCn 129.) 101 ...
Page 102
... Signal Description Figure 12-3. Note: 12.4.1 Input Description Table 12-1. Name OCRnRB[11 :0] OCRnSB[11 :0] OCRnRA[1 1:0] OCRnSA[11 :0] AT90PWM81 102 PSC External Block View CLK PLL CLK I/O SYnI n StopOut 12 OCRnR B[11:0] 12 OCRnSB[11:0] 12 OCRnR A[11:0] 12 OCRnSA[11:0] 4 OCRnR B[15:12] (Flank Width Modulation) 12 PICRn[11:0] IRQ PSC n StopIn SYnO ut 1. available only for PSC2 2 ...
Page 103
... Internal Outputs Description (1) Synchronization Output PSC n Input Capture Register Counter value at retriggering event PSC Interrupt Request : three sources, overflow, fault, and input capture ADC Synchronization (+ Amplifier Syncho. ) Stop Output (for synchronized mode) AT90PWM81 Register 4 bits Signal Signal (1) Signal Signal Type Width ...
Page 104
... Ramps illustrate the output of the PSC counter included in the waveform generators. Centered Mode is like a one ramp mode which count down up and down. Notice that the update of a new set of values is done regardless of ramp Mode at the top of the last ramp. AT90PWM81 104 1. See Figure 12-41 on page 131 2 ...
Page 105
... One moment for PSCn1 description with OT1 which gives the time of the whole moment 7734P–AVR–08/10 PSCn0 & PSCn1 Basic Waveforms in Four Ramp mode OCRnRA OCRnSA 0 On-Time 0 Dead-Time 0 PSC Cycle Minimal value for Dead-Time 0 and Dead-Time 1/Fclkpsc AT90PWM81 OCRnRB OCRnSB 0 On-Time 1 Dead-Time 1 105 ...
Page 106
... On-Time 0 = (OCRnRAH/L - OCRnSAH/L) * 1/Fclkpsc On-Time 1 = (OCRnRBH/L - OCRnSBH/L) * 1/Fclkpsc Dead-Time 0 = (OCRnSAH 1/Fclkpsc Dead-Time 1 = (OCRnSBH 1/Fclkpsc Note: 12.5.2.3 One Ramp Mode In One Ramp mode, PSCOUTn0 and PSCOUTn1 outputs can overlap each other. AT90PWM81 106 PSCn0 & PSCn1 Basic Waveforms in Two Ramp mode OCRnRA OCRnSA OCRnSB 0 0 ...
Page 107
... Center Aligned Mode In center aligned mode, the center of PSCn00 and PSCn01 signals are centered. 7734P–AVR–08/10 PSCn0 & PSCn1 Basic Waveforms in One Ramp mode OCRnRA OCRnSA 0 On-Time 0 Dead-Time 0 PSC Cycle Minimal value for Dead-Time 0 = 1/Fclkpsc AT90PWM81 OCRnRB OCRnSB On-Time 1 Dead-Time 1 107 ...
Page 108
... OCRnRAH/L is not used to control PSC Output waveform timing. Nevertheless, it can be useful to adjust ADC synchronization ( Figure 12-10. Run and Stop Mechanism in Centered Mode OCRnRB OCRnSB OCRnSA PSC Counter Run PSCOUTn0 PSCOUTn1 Note: AT90PWM81 108 PSCn0 & PSCn1 Basic Waveforms in Center Aligned Mode PSC Counter OCRnRB OCRnSB OCRnSA 0 On-Time 0 On-Time 1 PSCOUTn0 ...
Page 109
... See “PSC 2 Configuration Register – PCNF2” on page 135. 7734P–AVR–08/10 Regulation Loop Writting in Calculation PSC Registers Cycle Cycle Cycle Cycle With Set i With Set i With Set i With Set i page 134. AT90PWM81 Request for an Update Cycle With Set j End of Cycle 109 ...
Page 110
... The resulting resolution is Delta F equals 64MHz / 400 / 401 = 400 Hz. In enhanced mode, the output frequency is the average of the frame formed by the 16 consecutive cycles. f and f b1 Then the frequency resolution is divided by 16. In the example above, the resolution equals 25 Hz. AT90PWM81 110 Δ – ...
Page 111
... Note: The modulation is on the pulse width. and f where f is the nearest base frequency above the wanted frequency and The f and f frequencies are evenly distributed in the frame according to a predefined Table 12-6 AT90PWM81 ( ) = × ------------------------- - = PSC 16k k ...
Page 112
... The active time of PSCOUTn0 is given by the OT0 value. The active time of PSCOUTn1 is given by the OT1 value. Both of them are 12 bit values. Thanks to DT0 & DT1 to adjust the dead time between PSCOUTn0 and PSCOUTn1 active signals. AT90PWM81 112 Distribution the modulated frame ...
Page 113
... DT0 T1 SeeTable 12-6, “Distribution of fb2 in the modulated frame,” ----- = -------------------------------------------------------------------- - ( PSCn ----- = ------------------------------------------------------------------------------ ( PSCn T OT0 ----- - f AVERAGE 16 Table 12-14 AT90PWM81 f CLK_PSCn = -------------------------------------------------------------------- - ( ) OT0 + OT1 + DT0 + DT1 DT1 OT0 OT1 added on the PSCn0 signal while needed in the b2 f CLK_PSCn ) OT0 + OT1 + DT0 + DT1 f CLK_PSCn ...
Page 114
... OSR SA PSC start c ycle PAS DLKn(2:0) PSC input module B is shown on According to PSC n Input B Control Register (see Section “PSC n Input B Control Register – PFRCnB”, page 140), PSC n input B can act as a Retrigger or Fault input. AT90PWM81 114 Input 0 0 Blanking PSC n Input A ...
Page 115
... PAO CnB PSC n Input Digital 1 Filter 1 0 PFLTEnB CLK PSC 1 1 PCAEnB PELE VnB 4 PISELnB1 PISELnB0 PRFM nB3:0 CLK CLK AT90PWM81 Input Proces sing (retriggering ...) PSC PSC Output (Counter, Control PSCOUT n0 Wav eform (PSCOUT n1) Generator, ...) (PSCOUT2 PSC (PSCOUT2 115 ...
Page 116
... PSCn Input B is configurable thanks to a sense control block. PSCn Input B can be configured to do not act or to act on level or edge modes. PSCn Input B can be the Output of the analog comparator or the PSCINn input. As the period of the cycle decreases, the instantaneous frequency of the two outputs increases. AT90PWM81 116 On-Time 0 Dead-Time 0 Dead-Time 1 This example is given in “ ...
Page 117
... On-Time 0 Dead-Time 0 This example is given in “Input Mode 1” in “ ramp mode” See Figure 12-22. for details. On level mode, it’s possible to use PSC to generate burst by using Input Mode 3 or Mode 4 ( Figure 12-26. and Figure 12-27. for details.) AT90PWM81 On-Time 1 Dead-Time 1 Dead-Time 0 On-Time 1 Dead-Time 1 ...
Page 118
... Signal Polarity One can select the active edge (edge modes) or the active level (level modes) See PELEVnx bit descrip- tion in Section “PSC n Input A Control Register – PFRCnA”, page 14012.25.10. AT90PWM81 118 OFF is running. So thanks to PSC Asynchronous Output Control bit (PAOCnA/B), PSCnIN0/1 input is running ...
Page 119
... See “PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC” on page 126. 1001b Reserved : Do not use 1010b 1011b 1100b 1101b See “PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Deactivate 1110b Output” on page 127. Reserved : Do not use 1111b AT90PWM81 119 ...
Page 120
... PSC Input B is take into account during DT1 and OT1 only. It has no effect during DT0 and OT0. When PSC Input B event occurs, PSC releases PSCOUTn1, waits for PSC Input B inactive state and then jumps and executes DT0 plus OT0. AT90PWM81 120 DT0 ...
Page 121
... PSC Input B inactive state. Even if PSC Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always completely executed. 7734P–AVR–08/10 DT0 OT0 DT1 OT1 OT1 DT0 OT0 DT1 OT1 OT1 AT90PWM81 DT0 OT0 DT1 DT0 OT0 DT1 OT1 OT1 121 ...
Page 122
... When PSC Input B event occurs, PSC releases PSCnOUT1, jumps and executes DT0 plus OT0 plus DT1 while PSC Input active state. Even if PSC Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always completely executed. AT90PWM81 122 DT0 OT0 DT1 DT1 ...
Page 123
... PSCOUTn1 PSCn Input A or PSCn Input B 7734P–AVR–08/10 OT0 DT1 OT1 DT0 OT0 OT0 DT1 OT1 DT0 OT0 DT0 OT0 DT1 OT1 AT90PWM81 DT1 OT1 DT0 OT0 DT1 DT1 OT1 DT0 OT0 DT1 DT0 OT0 DT1 OT1 DT1 OT1 OT1 ...
Page 124
... OT0 PSCOUTn0 PSCOUTn1 PSCn Input A or PSCn Input B Note: Used in Fault mode 7, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1. AT90PWM81 124 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 1. Software action is the setting of the PRUNn bit in PCTLn register. ...
Page 125
... Note: In one ramp mode, the retrigger event on input A resets the whole ramp. So the PSC doesn’t jump to the opposite dead-time. 7734P–AVR–08/10 DT0 OT0 DT1 DT1 OT1 OT1 DT0 OT0 DT1 DT1 OT1 OT1 AT90PWM81 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 125 ...
Page 126
... Only the significative edge of Retrigger/Fault input is taken into account. Figure 12-36. PSC behavior versus PSCn Input B in Mode 9 DT0 OT0 PSCOUTn0 PSCOUTn1 PSCn Input B The retrigger event is taken into account only if it occurs during the corresponding On-Time. AT90PWM81 126 DT0 OT0 DT1 DT1 OT1 DT0 ...
Page 127
... The output of the PSC is set to an inactive state and the corresponding ramp is not aborted. The output stays in an inactive state while the Retrigger/Fault input is active. The PSC runs at constant frequency. 7734P–AVR–08/10 DT0 OT0 DT1 OT1 OT1 DT0 OT0 DT1 OT1 OT1 AT90PWM81 DT0 OT0 DT0 OT0 DT1 OT1 DT0 OT0 DT0 OT0 DT1 OT1 ...
Page 128
... Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. AT90PWM81 128 Available Input Modes according to Running Modes 1 Ramp Mode ...
Page 129
... If POS23 bit in PSOC2 register is set, PSCOUT23 duplicates PSCOUT20. Figure 12-39. PSCOUT22 and PSCOUT23 Outputs Waveform Generator A Waveform Generator B 7734P–AVR–08/10 Output Matrix versus ramp number Ramp 0 Ramp 1 POMV2A0 POMV2A1 POMV2B0 POMV2B1 Output Matrix AT90PWM81 Ramp 2 Ramp 3 POMV2A2 POMV2A3 POMV2B2 POMV2B3 PSCOUT20 0 PSCOUT22 1 POS22 POS23 1 PSCOUT23 0 ...
Page 130
... As each PSC can be dedicated for one function, each PSC has its own interrupt system (vector ...) List of interrupt sources: • Counter reload (end of On Time 1) • End of Enhanced Cycle • PSC Input event (active edge or at the beginning of level configured event) • PSC Mutual Synchronization Error AT90PWM81 130 and Table 12-12 on page 134. OCRnRA ...
Page 131
... PSC Synchronization Note : In AT90PWM81, this feature is not relevant and PRUN2, PARUN2 are stuck at zero PSC can be synchronized together. In this case, two waveform alignments are possible: • The waveforms are center aligned in the Center Aligned mode if master and slaves are all with the same PSC period (which is the natural use). • ...
Page 132
... PPREn1/0 bits in PSC n Control Register (PCTLn) are used to select the divide factor of the clock. Table 12-10. PCLKSELn 12.24 Interrupts This section describes the specifics of the interrupt handling as performed in AT90PWM81. AT90PWM81 132 1 PLL CK 0 I/O PCLKSELn Output Clock versus Selection and Prescaler PPREn1 PPREn0 ...
Page 133
... Send signal on leading edge of PSCOUTn0 (match with OCRnSA) Send signal on trailing edge of PSCOUTn0 (match with OCRnRA or 1 fault/retrigger on part A) 0 Send signal on leading edge of PSCOUTn1 (match with OCRnSB) Send signal on trailing edge of PSCOUTn1 (match with OCRnRB or 1 fault/retrigger on part B) AT90PWM81 POEN2D POEN2B POEN2C POEN2A ...
Page 134
... Bit Read/Write Initial Value 12.25.3 Output Compare RA Register – OCRnRAH and OCRnRAL Bit Read/Write Initial Value AT90PWM81 134 Synchronization Source Description in Centered Mode PSYNCn0 Description Send signal on match with OCRnRA (during counting down of PSC). The min 0 value of OCRnRA must be 1. Send signal on match with OCRnRA (during counting up of PSC). The min value 1 of OCRnRA must be 1 ...
Page 135
... OCRnRB[15:12] OCRnRB[7: PFIFTY2 PALOCK2 PLOCK2 PMODE21 PMODE20 POP2 R/W R/W R/W R AT90PWM81 OCRnSB[11: OCRnRB[11: PCLKSEL2 POME2 R/W R/W R/W R/W 0 ...
Page 136
... Defines the modes for Analog signal synchronization delay or Input Blanking. Table 12-14. Analog signal synchronization or Input Blanking Mode Selection PASDLKn2 PASDLKn1 AT90PWM81 136 PSC n Mode Selection PMODEn0 Description 0 One Ramp Mode 1 Two Ramp Mode 0 Four Ramp Mode 1 Center Aligned Mode ...
Page 137
... Flank Width Modulation operates (On-Time 0 and On-Time 1 1). 0 Flank Width Modulation operates on SB (Dead-Time 1 only) Flank Width Modulation operates on SB +SA (Dead-Time 0 and Dead- 1 Time 1). Note: In one ramp mode, changing SA or SA+SB also affect On-Time ; see PSCn0 & PSCn1 Basic Wave- forms in One Ramp mode AT90PWM81 (1) . 137 ...
Page 138
... Bit 1– PISELnA1: PSC n Input Select for part A Together with PISELnA0, defines active signal on PSC part A. Table 12-18. PISELnA1 AT90PWM81 138 PSC edge & level input Selection PELEVnA0 Description The falling edge or low level of selected input generates the significative 0 event for retrigger or fault function ...
Page 139
... PASDLYn[7: PPRE21 PPRE20 PBFM20 PAOC2B R/W R/W R/W R PSC n Prescaler Selection PPREn0 Description 0 No divider on PSC input clock AT90PWM81 PAOC2A PARUN2 PCCYC2 PRUN2 R/W R/W R/W R PASDLYn PCTL2 139 ...
Page 140
... PSC n Input A Control Register – PFRCnA Bit Read/Write Initial Value 12.25.11 PSC n Input B Control Register – PFRCnB Bit Read/Write Initial Value AT90PWM81 140 PSC n Prescaler Selection PPREn0 Description 1 Divide the PSC input clock Divide the PSC input clock Divide the PSC clock by 64 ...
Page 141
... PSC Input Mode 5: Stop signal and Insert Dead-Time PSC Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait. PSC Input Mode 7: Halt PSC and Wait for Software Action PSC Input Mode 8: Edge Retrigger PSC PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC AT90PWM81 Table 12-18 on Table 12- 141 ...
Page 142
... Bit 6 – POMV2B2: Output Matrix Output B Ramp 2 This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 2 • Bit 5 – POMV2B1: Output Matrix Output B Ramp 1 This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 1 AT90PWM81 142 Level Sensitivity and Fault Mode Operation Description ...
Page 143
... Bit 0 – PEOPEn : PSC n End Of Cycle Interrupt Enable When this bit is set, an interrupt is generated when PSC reaches the end of the whole cycle. 7734P–AVR–08/ PSEIE2 PEVE2B R R R/W R AT90PWM81 PEVE2A - PEOEPE2 PEOPE2 R/W R R/W R PIM2 143 ...
Page 144
... Retrigger/Fault block A occurs. Must be cleared by software by writing a one to its location. This bit can be read even if the corresponding interrupt is not enabled (PEVEnA bit = 0). • Bit 2:1 – PRNn1:0 : PSC n Ramp Number Memorization of the ramp number when the last PEVnA or PEVnB occurred . AT90PWM81 144 ...
Page 145
... PSCOUT & PSCOUTR Reset 4 Value PSC & PSCR Inputs Reset 3 Behavior (1) 2 Brown-out Detector trigger level (1) 1 Brown-out Detector trigger level (1) 0 Brown-out Detector trigger level 1. See Table 7-2 on page 52 for BODLEVEL Fuse decoding AT90PWM81 Default Value (unprogrammed) 0 (programmed) 1 (unprogrammed) 145 ...
Page 146
... If PSCINRB fuse equals 1 (unprogrammed), PSC & PSCR input keep a standard port behavior. If PSCINRB fuse equals 0 (programmed), PSC & PSCR input pull-up are forced while the reset is active. Affected pins are PSCIN2, PSCINr, PSCIN2A, PSCINrA. To prevent any conflict on PD1, this fuse has no effect on PSCINrB. AT90PWM81 146 7734P–AVR–08/10 ...
Page 147
... Output” to drive single power transistor (DC/DC converter, PFC, ...) The PSCR has two inputs the purpose of which is to provide means to act directly on the generated waveforms: • Current sensing regulation • Zero crossing retriggering • Demagnetization retriggering • Fault input 7734P–AVR–08/10 AT90PWM81 147 ...
Page 148
... The PSCR is seen as two symmetrical entities. One part named part A which generates the output PSCOUTr0 and the second one named part B which generates the PSCOUTr1 output. Each part has its own PSCR Input Module to manage selected input. AT90PWM81 148 Power Stage Controller Block Diagram ...
Page 149
... OCRrR A[11:0] 12 OCRrSA[11:0] 12 PICRr[11:0] IRQ PSC r Internal Inputs Description Compare Value which Reset Signal on Part B (PSCOUTr1) Compare Value which Set Signal on Part B (PSCOUTr1) Compare Value which Reset Signal on Part A (PSCOUTr0) AT90PWM81 PSCOUT r0 PSCOUT r1 3 PSCINr Aralog Comparator Output PSCrASY Type Width Register ...
Page 150
... Name PSCOUTr0 PSCOUTr1 Table 13-4. Name PICRr [11:0] IRQPSCr PSCrASY AT90PWM81 150 Description Compare Value which Set Signal on Part A (PSCOUTr0) Clock Input from I/O clock Clock Input from PLL Block Inputs Description Input 0 used for Retrigger or Fault functions Input 1 used for Retrigger or Fault functions ...
Page 151
... OT1 value. Both of them are 12 bit values. Thanks to DT0 & DT1 to adjust the dead time between PSCOUTn0 and PSCOUTn1 active signals. 7734P–AVR–08/10 Cycle Presentation & 4 Ramp Mode PSC Cycle Sub-Cycle A Sub-Cycle B Ramp A0 Ramp A1 Ramp B0 Ramp B1 Ramp A Ramp B AT90PWM81 UPDATE 151 ...
Page 152
... PSCOUTn1 The input clock of PSCR is given by CLKPSC. PSCOUTr0 and PSCOUTr1 signals are defined by On-Time 0, Dead-Time 0, On-Time 1 and Dead-Time 1 values with : On-Time 0 = OCRrRAH/L * 1/Fclkpsc On-Time 1 = OCRrRBH/L * 1/Fclkpsc Dead-Time 0 = (OCRrSAH 1/Fclkpsc Dead-Time 1 = (OCRrSBH 1/Fclkpsc Note: AT90PWM81 152 ----------------------------- - = PSCn PSCnCycle PSCr0 & PSCr1 Basic Waveforms in Four Ramp mode ...
Page 153
... In One Ramp mode, PSCOUTr0 and PSCOUTr1 outputs can overlap each other. 7734P–AVR–08/10 PSCr0 & PSCr1 Basic Waveforms in Two Ramp mode OCRnRA OCRnSA 0 0 On-Time 0 Dead-Time 0 PSC Cycle Minimal value for Dead-Time 0 and Dead-Time 1 = 1/Fclkpsc AT90PWM81 OCRnRB OCRnSB On-Time 1 Dead-Time 1 153 ...
Page 154
... To avoid asynchronous and incoherent values in a cycle update of one of several values is necessary, all values are updated at the same time at the end of the cycle by the PSC. The new set of values is calcu- lated by software and the update is initiated by software. AT90PWM81 154 PSCr0 & PSCr1 Basic Waveforms in One Ramp mode ...
Page 155
... Update at the end of complete PSCR cycle. Regulation Loop Writting in Calculation PSC Registers Cycle Cycle Cycle Cycle With Set i With Set i With Set i With Set i page 172. 13.23.8page AT90PWM81 Request for an Update Cycle With Set j End of Cycle 175), PSCrIN0/1 input can act has a Retrigger or 155 ...
Page 156
... The polarity of PSCr Input A is configu- rable thanks to a sense control block. PSCr Input A can be the Output of the analog comparator or the PSCINr input. As the period of the cycle decreases, the instantaneous frequency of the two outputs increases. AT90PWM81 156 PSCR Input Module PAO CrA ...
Page 157
... PSCOUTr0 retriggered by PSCr Input A (Edge Retriggering) On-Time 0 Dead-Time 0 Dead-Time 1 This example is given in “Input Mode 8” in “ ramp mode” See Figure 13-25. for details. On-Time 0 Dead-Time 0 This example is given in “Input Mode 1” in “ ramp mode” See Figure 13-14. for details. AT90PWM81 On-Time 1 On-Time 1 Dead-Time 1 157 ...
Page 158
... PSCOUTn1 PSCn Input B (high level) PSCn Input B (low level) Note: 13.8.3.1 Burst Generation Note: AT90PWM81 158 On-Time 0 Dead-Time 0 Dead-Time 1 This example is given in “Input Mode 8” in “ ramp mode” See Figure 13-25. for details. On-Time 0 Dead-Time 0 Dead-Time 1 This example is given in “Input Mode 1” in “ ramp mode” See Figure 13-14. for details. ...
Page 159
... Section “PSCR Input A Control Register – PFRC0A”, page 17513.23.8. 7734P–AVR–08/10 OFF is running. So thanks to PSCR Asynchronous Output Control bit (PAOCrA/B), PSCrIN0/1 input is running. PSCR CLK PSC Digital Filter 4 x CLK PSC PSC Input Module X AT90PWM81 BURST PSCn Input Ouput PSCOUTnX Stage PIN 159 ...
Page 160
... Notice: All following examples are given with rising edge or high level active inputs. AT90PWM81 160 PSCR Input Mode Operation PRFM3:0 Description PSCr Input has no action on PSCR output 0000b 13.9See “PSCR Input Mode 1: Stop signal, Jump to Opposite Dead-Time and 0001b Wait” ...
Page 161
... When PSCR Input B event occurs, PSCR releases PSCOUTr1, waits for PSCR Input B inactive state and then jumps and executes DT0 plus OT0. 7734P–AVR–08/10 DT0 OT0 OT1 DT0 OT0 DT1 OT1 OT1 AT90PWM81 DT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 OT1 ...
Page 162
... When PSCR Input B event occurs, PSCR releases PSCOUTr1, jumps and executes DT0 plus OT0 and then waits for PSCR Input B inactive state. Even if PSCR Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always completely executed. AT90PWM81 162 DT0 OT0 DT1 OT1 ...
Page 163
... Even if PSCR Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always completely executed. 7734P–AVR–08/10 DT0 OT0 DT1 DT1 OT1 OT1 DT0 OT0 DT1 DT0 OT0 OT1 AT90PWM81 DT1 DT0 OT0 DT1 OT1 DT0 OT0 DT0 OT0 DT1 OT1 OT1 ...
Page 164
... PSCr Input A or PSCr Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1. 13.13 PSCR Input Mode 5: Stop signal and Insert Dead-Time Figure 13-22. PSCR behavior versus PSCr Input A in Fault Mode 5 DT0 OT0 PSCOUTn0 PSCOUTn1 PSCn Input A or PSCn Input B AT90PWM81 164 DT1 OT1 DT0 OT0 OT0 DT1 OT1 DT0 ...
Page 165
... Used in Fault mode 7, PSCr Input A or PSCr Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1. 7734P–AVR–08/10 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 1. Software action is the setting of the PRUNn bit in PCTLr register. AT90PWM81 DT0 OT0 DT1 OT1 DT1 DT0 OT0 DT1 Software Action (1) ...
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... The output frequency is modulated by the occurrence of significative edge of retriggering input. The retrigger event is taken into account only if it occurs during the corresponding On-Time. Note: In one ramp mode, the retrigger event on input A resets the whole ramp. So the PSCR doesn’t jump to the opposite dead-time. AT90PWM81 166 DT0 OT0 DT1 ...
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... PSCOUTn1 PSCn Input B The retrigger event is taken into account only if it occurs during the corresponding On-Time. 7734P–AVR–08/10 DT0 OT0 DT1 DT1 OT1 DT0 OT0 DT1 OT1 AT90PWM81 DT0 OT0 OT1 DT1 DT0 OT0 DT1 OT1 DT1 OT1 OT1 167 ...
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... The output is deactivated while retriggering input is active. The output of the PSCR is set to an inactive state and the corresponding ramp is not aborted. The output stays in an inactive state while the Retrigger/Fault input is active. The PSCR runs at constant frequency. AT90PWM81 168 DT0 OT0 ...
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... Available Input Modes according to Running Modes 1 Ramp Mode Valid Do not use Do not use Valid Do not use Do not use Valid Valid Valid Do not use Valid Do not use AT90PWM81 2 Ramp Mode 4 Ramp Mode Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid ...
Page 170
... PCLKSELr bit in PSCR Configuration register (PCNFr) is used to select the clock source. PPREr1/0 bits in PSCR Control Register (PCTLr) are used to select the divide factor of the clock. Table 13-7. PCLKSELr AT90PWM81 170 CLK 1 PLL CK CLK 0 I/O PCLKSELr Output Clock versus Selection and Prescaler PPREr1 ...
Page 171
... Interrupts This section describes the specifics of the interrupt handling as performed in AT90PWM81. 13.22.1 List of Interrupt Vector The PSCR provides 3 interrupt vectors • PSC0EC (End of Cycle): When enabled and when a match with OCRrRB occurs • PSC0EEC (End of Enhanced Cycle): When enabled and when a match with OCRrRB occurs at the 15th enhanced cycle • ...
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... Bit Read/Write Initial Value 13.23.4 Output Compare SB Register – OCR0SBH and OCR0SBL Bit Read/Write Initial Value AT90PWM81 172 Synchronization Source Description in One/Two/Four Ramp Modes PSYNC00 Description 0 Send signal on leading edge of PSCOUT00 (match with OCR0SA) Send signal on trailing edge of PSCOUT00 (match with OCR0RA or ...
Page 173
... Select the mode of PSC. 7734P–AVR–08/ OCR0RB[15:12] OCR0RB[7: PFIFTY0 PALOCK0 PLOCK0 PMODE01 PMODE00 POP0 R/W R/W R/W R AT90PWM81 OCR0RB[11: PCLKSEL0 - R/W R/W R/W R OCR0RBH OCR0RBL PCNF0 173 ...
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... Bit 7:6 – PPRE01:0 : PSCR Prescaler Select This two bits select the PSCR input clock division factor. All generated waveform will be modified by this factor. Table 13-12. PPRE01 AT90PWM81 174 PSCR Mode Selection PMODE00 Description 0 One Ramp Mode 1 Two Ramp Mode ...
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... Note: In one ramp mode, changing SA or SA+SB also affect On-Time ; see PSCr0 & PSCr1 Basic Wave- forms in One Ramp mode PCAE0A PISEL0A0 PELEV0A PFLTE0A R/W R/W R/W R PCAE0B PISEL0B0 PELEV0B PFLTE0B R/W R/W R/W R AT90PWM81 PRFM0A3 PRFM0A2 PRFM0A1 PRFM0A0 PFRC0A R/W R/W R/W R PRFM0B3 PRFM0B2 PRFM0B1 PRFM0B0 PFRC0B R/W R/W R/W R (1) . 175 ...
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... AT90PWM81 176 and Table 13-9 on page 171 Level Sensitivity and Fault Mode Operation Description No action, PSCR Input is ignored PSCR Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait PSCR Input Mode 2: Stop signal, Execute Opposite Dead-Time and Wait PSCR Input Mode 3: Stop signal, Execute Opposite while Fault active PSCR Input Mode 4: Deactivate outputs without changing timing ...
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... Output Reserved (do not use PCST0 – – – PICR0[7: PEVE0B R AT90PWM81 PICR0[11: PEVE0A - PEOEPE0 PEOPE0 R R PICR0H PICR0L PIM0 177 ...
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... Retrigger/Fault block A occurs. Must be cleared by software by writing a one to its location. This bit can be read even if the corresponding interrupt is not enabled (PEVE0A bit = 0). • Bit 2:1 – PRN01:0 : PSCR Ramp Number Memorization of the ramp number when the last PEV0A or PEV0B occurred. AT90PWM81 178 ...
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... The last event which has generated an interrupt occurred during ramp 1 1 The last event which has generated an interrupt occurred during ramp 2 0 The last event which has generated an interrupt occurred during ramp 3 1 The last event which has generated an interrupt occurred during ramp 4 AT90PWM81 179 ...
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... Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode 14.2 Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90PWM81 and peripheral devices or between several AVR devices. The AT90PWM81 SPI includes the following features Figure 14-1. Note: AT90PWM81 180 ...
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... In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the frequency of the SPI clock should never exceed f 7734P–AVR–08/10 SPI Master-slave Interconnection AT90PWM81 Figure 14-2. The system con- SHIFT ENABLE /4 ...
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... DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB2, replace DD_MOSI with DDB2 and DDR_SPI with DDRB. AT90PWM81 182 14-1. For more details on automatic port overrides, refer to ...
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... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. The example code assumes that the part specific header file is included. AT90PWM81 183 ...
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... SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high. AT90PWM81 184 (1) r17,(1< ...
Page 185
... Table 14-2. CPOL=0, CPHA=0 CPOL=0, CPHA=1 CPOL=1, CPHA=0 CPOL=1, CPHA=1 7734P–AVR–08/10 CPOL Functionality Leading Edge Sample (Rising) Setup (Rising) Sample (Falling) Setup (Falling) AT90PWM81 Figure 14-3 and Figure Table 14-3 and Table 14-4, as done below: Trailing eDge SPI Mode Setup (Falling) 0 Sample (Falling) ...
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... This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set. • Bit 6 – SPE: SPI Enable When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations. AT90PWM81 186 SPI Transfer Format with CPHA = 0 SCK (CPOL = 0) ...
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... Relationship Between SCK and the Oscillator Frequency SPR1 AT90PWM81 Trailing Edge Rising Falling Falling Rising for an example. The CPOL functionality is sum- Trailing Edge Sample Setup Sample frequency f is shown in the following table: IO clkio SPR0 SCK Frequency f ...
Page 188
... When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Mas- ter mode (see When the SPI is configured as Slave, the SPI is only guaranteed to work at f The SPI interface on the AT90PWM81 is also used for program memory and EEPROM downloading or uploading. See 14.5.3 SPI Data Register – ...
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... Low Power Consumption 15.2 On Chip voltage Reference and Temperature sensor overview A low power band-gap reference provides AT90PWM81 with an accurate On-chip Bandgap voltage of 1.100 V (Vbg). Then when SW1 is off and SW2/SW3 is on, the bandgap voltage is multiplied and generates the internal reference VREF of 2.56V. This reference voltage is used as reference for the ADC, the DAC and can use ...
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... BG Calibr ation Reg isters BGCC R, BGCRR AT90PWM81 has an On-chip temperature sensor for monitoring the die temperature. A voltage Propor- tional-To-Absolute-Temperature, VPTAT, is generated in the voltage reference circuit and after buffering, is connected to the ADC multiplexer. This temperature sensor can be used for runtime compen- sation of temperature drift in both the voltage reference and the On-chip Oscillator ...
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... Vbg curve to the lowest possible temperature. 7734P–AVR–08/ AT90PWM81 BGCC3 BGCC2 BGCC1 BGCC0 R/W R/W R/W R BGCR3 BGCR2 BGCR1 BGCR0 R/W R/W R/W R Figure 15-2 BGCCR ...
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... When the temperature sensor is enabled, the ADC converter can be used in single conversion mode to measure the voltage over the temperature sensor. The amplifier allows to charge the ADC sample capacitor at full CKadc clock speed. The measured voltage has a linear relationship to temperature as AT90PWM81 192 Temperature range of interest ...
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... Temperature vs. Sensor Output Voltage (Typical Case) -40°C 25°C 600 762 240 305 243. 243. AT90PWM81 105°C 125°C 1012 405 See “Reading the Signature Row See “Reading the Signature 193 ...
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... Generation of Configurable Interrupts 16.2 Overview The AT90PWM81 features 3 fast analog comparators. Each comparator has a dedicated input on the positive input, and the negative input of each comparator can be configured as: • a steady value among the 4 internal reference levels defined by the Vref selected thanks to the REFS1:0 bits in ADMUX register. • ...
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... Ref e rence /2.13 /3.20 /6.40 REFS1 REFS0 +REFS1 1. .Refer to Figure 2-1 on page 3 and for Analog Comparator pin placement 2. The voltage on Vref is defined in 17-3 ”ADC Voltage Reference Selection” on page 217 AT90PWM81 AC1 Interrupt Sensitivit y Con trol - AC1 IE AC1 IS1 AC1 IS0 AC1 EN AC1 ICE AC2 H ...
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... Analog Comparator Register Description Each analog comparator has its own control register. A dedicated register has been designed to consign the outputs and the flags of the 3 analog comparators. AT90PWM81 196 Comparator PSC links + ACM P1 - ...
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... Band Gap voltage 0 1 DAC result 1 0 Analog Comparator Negative Input (ACMPM1 pin Analog Comparator Negative Input (ACMPM pin) AT90PWM81 AC1M2 AC1M1 AC1M0 R/W R/W R/W R AC1CON 197 ...
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... Bit 2, 1, 0– AC2M2, AC2M1, AC2M0: Analog Comparator 2 Multiplexer register These 3 bits determine the input of the negative input of the analog comparator. The different setting are shown in Table 16-4. AC2M2 AT90PWM81 198 AC2EN AC2IE AC2IS1 AC2IS0 R/W R/W R/W ...
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... Band Gap voltage 0 1 DAC result 1 0 Analog Comparator Negative Input (ACMPM3 pin Analog Comparator Negative Input (ACMPM pin) AT90PWM81 AC3OEA AC3M2 AC3M1 AC3M0 - R/W R/W R AC3CON 199 ...
Page 200
... Bit 2, 1, 0– ACnH2, ACnH1, ACnH0: Analog Comparator n Hysteresis select These 3 bits determine the hysteresis value of the analog comparator The different setting are shown in Table 16-7. AC1M2 AT90PWM81 200 ACnOI ACnOE R/W R (“ ...