AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet - Page 239

• Manufacturer Part Number: AT90PWM81
• Manufacturer: Atmel Corporation

Specifications of AT90PWM81

• Flash (kbytes): 8 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

20.6
7734P–AVR–08/10
Addressing the Flash During Self-Programming
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles
executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high
part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion
of a Page Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during
the entire Page Write operation if the NRWW section is addressed.
• Bit 1 – PGERS: Page Erase
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles
executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0
are ignored. The PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is
executed within four clock cycles. The CPU is halted during the entire Page Write operation if the
NRWW section is addressed.
• Bit 0 – SPMEN: Self Programming Enable
This bit enables the SPM instruction for the next four clock cycles. If written to one together with either
RWWSRE, BLBSET, PGWRT or PGERS, the following SPM instruction will have a special meaning,
see description above. If only SPMEN is written, the following SPM instruction will store the value in
R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The
SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed
within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high until the opera-
tion is completed.
Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower five
bits will have no effect.
The Z-pointer is used to address the SPM commands.
Since the Flash is organized in pages (see
as having two different sections. One section, consisting of the least significant bits, is addressing the
words within a page, while the most significant bits are addressing the pages. This is1 shown in
3. Note that the Page Erase and Page Write operations are addressed independently. Therefore it is of
major importance that the Boot Loader software addresses the same page in both the Page Erase and Page
Write operation. Once a programming operation is initiated, the address is latched and the Z-pointer can
be used for other operations.
The only SPM operation that does not use the Z-pointer is Setting the Boot Loader Lock bits. The content
of the Z-pointer is ignored and will have no effect on the operation. The LPM instruction does also use the
Z-pointer to store the address. Since this instruction addresses the Flash byte-by-byte, also the LSB (bit
Z0) of the Z-pointer is used.
Bit
ZH (R31)
ZL (R30)
15
Z15
Z7
7
14
Z14
Z6
6
13
Z13
Z5
5
Table 21-11 on page
12
Z12
Z4
4
11
Z11
Z3
3
254), the Program Counter can be treated
10
Z10
Z2
2
9
Z9
Z1
1
AT90PWM81
8
Z8
Z0
0
Figure 20-
239