AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet - Page 34

• Manufacturer Part Number: AT90PWM81
• Manufacturer: Atmel Corporation

Specifications of AT90PWM81

• Flash (kbytes): 8 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

Table 5-9.
5.2.7
34
CKSEL3..0
0100
0101
0001
AT90PWM81
Clock Output Buffer
Start-up Times when the PLL is selected as system clock
SUT1..0
00
01
10
00
01
10
00
01
10
11
11
The PLL is locked on the source oscillator which must remains close to 8 MHz to assure proper lock of
the PLL.
Both internal RC Oscillator and PLL are switched off in Power-down and Standby sleep modes
Figure 5-4.
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse or
COUT bit of CLKSELR register has to be programmed. This mode is suitable when the chip clock is used
to drive other circuits on the system. Note that the clock will not be output during reset and the normal
operation of I/O pin will be overridden when the fuses are programmed. Any clock source can be selected
when the clock is output on CLKO. If the System Clock Prescaler is used, it is the divided system clock
that is output.
Start-up Time from Power-down
16K CK
16K CK
16K CK
16K CK
16K CK
1K CK
1K CK
1K CK
1K CK
1K CK
1K CK
PCK Clocking System
XT AL1
XT AL2
RC OSCILLATOR
OSCCAL
8 MHz
OSCILLATORS
CKSEL3..0
Additional Delay from Reset
14CK + 64 ms
14CK + 64 ms
14CK + 64 ms
(V
14CK + 4 ms
14CK + 4 ms
14CK + 4 ms
14CK + 4 ms
CC
14CK
14CK
14CK
14CK
PLLE
= 5.0V)
PLL
*N
PLLF3..0
Detector
Lock
DIVIDE
BY 4
External Crystal or resonator
Internal RC Oscillator
External Clock
Clock Source
CLK
PLOCK
CK
7734P–AVR–08/10
PLL
SOURCE