ATmega1284RZAP Atmel Corporation, ATmega1284RZAP Datasheet

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ATmega1284RZAP

Manufacturer Part Number
ATmega1284RZAP
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega1284RZAP

Flash (kbytes)
128 Kbytes
Max. Operating Frequency
20 MHz
Max I/o Pins
32
Spi
3
Twi (i2c)
1
Uart
2
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Crypto Engine
No
Sram (kbytes)
16
Eeprom (bytes)
4096
Operating Voltage (vcc)
1.8 to 3.6
Timers
3
Frequency Band
2.4 GHz
Max Data Rate (mb/s)
0.25
Antenna Diversity
No
External Pa Control
No
Power Output (dbm)
3
Receiver Sensitivity (dbm)
-101
Receive Current Consumption (ma)
16.0
Transmit Current Consumption (ma)
17.0
Link Budget (dbm)
104
Features
High-performance, Low-power AVR
Advanced RISC Architecture
Nonvolatile Program and Data Memories
JTAG (IEEE std. 1149.1 Compliant) Interface
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltages
Speed Grades
Power Consumption at 1 MHz, 1.8V, 25°C
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– On-chip 2-cycle Multiplier
– 128K Bytes of In-System Self-Programmable Flash
– Optional Boot Code Section with Independent Lock Bits
– 4K Bytes EEPROM
– 16K Bytes Internal SRAM
– Programming Lock for Software Security
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– Two 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel, 10-bit ADC
– Byte-oriented Two-wire Serial Interface
– Two Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF
– 1.8 - 5.5V for ATmega1284P
– 0 - 4 MHz @ 1.8 - 5.5V
– 0 - 10 MHz @ 2.7 - 5.5V
– 0 - 20 MHz @ 4.5 - 5.5V
– Active: 0.4 mA
– Power-down Mode: 0. 1 µA
– Power-save Mode: 0.7 µA (Including 32 kHz RTC)
Mode
and Extended Standby
Endurance: 10,000 Write/Erase Cycles
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
Endurance: 100,000 Write/Erase Cycles
Differential mode with selectable gain at 1x, 10x or 200x
®
8-bit Microcontroller
8-bit
Microcontroller
with 128K Bytes
In-System
Programmable
Flash
ATmega1284P
Preliminary
Summary
8059DS–AVR–11/09

Related parts for ATmega1284RZAP

ATmega1284RZAP Summary of contents

Page 1

Features • High-performance, Low-power AVR • Advanced RISC Architecture – 131 Powerful Instructions – Most Single-clock Cycle Execution – General Purpose Working Registers – Fully Static Operation – MIPS Throughput at 20 MHz – ...

Page 2

Pin Configurations Figure 1-1. Note: ATmega1284P 2 Pinout ATmega1284P (PCINT8/XCK0/T0) PB0 (PCINT9/CLKO/T1) PB1 (PCINT10/INT2/AIN0) PB2 (PCINT11/OC0A/AIN1) PB3 (PCINT12/OC0B/SS) PB4 (PCINT13/ICP3/MOSI) PB5 (PCINT14/OC3A/MISO) PB6 (PCINT15/OC3B/SCK) PB7 RESET VCC GND XTAL2 XTAL1 (PCINT24/RXD0/T3) PD0 (PCINT25/TXD0) PD1 (PCINT26/RXD1/INT0) PD2 (PCINT27/TXD1/INT1) PD3 (PCINT28/XCK1/OC1B) ...

Page 3

Overview The ATmega1284P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega1284P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to ...

Page 4

The ATmega1284P provides the following features: 128K bytes of In-System Programmable Flash with Read-While-Write capabilities, 4K bytes EEPROM, 16K bytes SRAM, 32 general pur- pose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), three flexible Timer/Counters with ...

Page 5

Port B (PB7:PB0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B ...

Page 6

Resources A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr. ATmega1284P 6 8059DS–AVR–11/09 ...

Page 7

Register Summary Address Name Bit 7 (0xFF) Reserved - (0xFE) Reserved - (0xFD) Reserved - (0xFC) Reserved - (0xFB) Reserved - (0xFA) Reserved - (0xF9) Reserved - (0xF8) Reserved - (0xF7) Reserved - (0xF6) Reserved - (0xF5) Reserved - ...

Page 8

Address Name Bit 7 (0xC0) UCSR0A RXC0 (0xBF) Reserved - (0xBE) Reserved - (0xBD) TWAMR TWAM6 (0xBC) TWCR TWINT (0xBB) TWDR (0xBA) TWAR TWA6 (0xB9) TWSR TWS7 (0xB8) TWBR (0xB7) Reserved - (0xB6) ASSR - (0xB5) Reserved - (0xB4) OCR2B ...

Page 9

Address Name Bit 7 (0x7E) DIDR0 ADC7D (0x7D) Reserved - (0x7C) ADMUX REFS1 (0x7B) ADCSRB - (0x7A) ADCSRA ADEN (0x79) ADCH (0x78) ADCL (0x77) Reserved - (0x76) Reserved - (0x75) Reserved - (0x74) Reserved - (0x73) PCMSK3 PCINT31 (0x72) Reserved ...

Page 10

Address Name Bit 7 0x1C (0x3C) EIFR - 0x1B (0x3B) PCIFR - 0x1A (0x3A) Reserved - 0x19 (0x39) Reserved - 0x18 (0x38) TIFR3 - 0x17 (0x37) TIFR2 - 0x16 (0x36) TIFR1 - 0x15 (0x35) TIFR0 - 0x14 (0x34) Reserved - ...

Page 11

Instruction Set Summary Mnemonics Operands ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract ...

Page 12

Mnemonics Operands BRVC k Branch if Overflow Flag is Cleared BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register CBI P,b Clear Bit in I/O Register ...

Page 13

Mnemonics Operands SPM Store Program Memory IN Rd Port OUT P, Rr Out Port PUSH Rr Push Register on Stack POP Rd Pop Register from Stack MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK ...

Page 14

Ordering Information 6.1 ATmega1284P (3) Speed (MHz) Power Supply 20 1.8 - 5.5V Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. ...

Page 15

Packaging Information 7.1 44A PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions ...

Page 16

A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm ...

Page 17

D Marked Pin TOP VIEW BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3. Package Drawing Contact: packagedrawings@atmel.com 8059DS–AVR–11/09 E Pin #1 Corner Pin #1 Option A 1 ...

Page 18

Errata 8.1 ATmega1284P Rev known Errata. ATmega1284P 18 8059DS–AVR–11/09 ...

Page 19

Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 9.1 Rev. 8059D - 11/ ...

Page 20

... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2009 Atmel Corporation. All rights reserved. Atmel trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia Atmel Europe Unit 1-5 & ...

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