IC AVR MCU 2.4GHZ XCEIVER 64QFN

ATMEGA128RFA1-ZU

Manufacturer Part NumberATMEGA128RFA1-ZU
DescriptionIC AVR MCU 2.4GHZ XCEIVER 64QFN
ManufacturerAtmel
SeriesATMEGA
ATMEGA128RFA1-ZU datasheets
 


Specifications of ATMEGA128RFA1-ZU

Frequency2.4GHzData Rate - Maximum2Mbps
Modulation Or Protocol802.15.4 ZigbeeApplicationsGeneral Purpose
Power - Output3.5dBmSensitivity-100dBm
Voltage - Supply1.8 V ~ 3.6 VCurrent - Receiving12.5mA
Current - Transmitting14.5mAData InterfacePCB, Surface Mount
Memory Size128kB Flash, 4kB EEPROM, 16kB RAMAntenna ConnectorPCB, Surface Mount
Operating Temperature-40°C ~ 85°CPackage / Case64-VFQFN, Exposed Pad
Rf Ic Case StyleQFNNo. Of Pins64
Supply Voltage Range1.8V To 3.6VOperating Temperature Range-40°C To +85°C
SvhcNo SVHC (15-Dec-2010)Rohs CompliantYes
Processor SeriesATMEGA128xCoreAVR8
Data Bus Width8 bitProgram Memory TypeFlash
Program Memory Size128 KBData Ram Size16 KB
Interface TypeJTAGMaximum Clock Frequency16 MHz
Number Of Programmable I/os38Number Of Timers6
Operating Supply Voltage1.8 V to 3.6 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsEWAVR, EWAVR-BL
Development Tools By SupplierATAVR128RFA1-EK1Lead Free Status / RoHS StatusLead free / RoHS Compliant
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Features
High-performance, Low-power Atmel
Advanced RISC Architecture
– 133 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers + Peripheral Control Registers
– Fully Static Operation
– Up to 16MIPS Throughput at 16MHz
– On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory segments
– 128Kbytes of In-System Self-programmable Flash program memory
– 4Kbytes EEPROM
– 4Kbytes Internal SRAM
– Write/Erase cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Up to 64Kbytes Optional External Memory Space
– Programming Lock for Software Security
– SPI Interface for In-System Programming
JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and
Capture Mode
– Real Time Counter with Separate Oscillator
– Two 8-bit PWM Channels
– 6 PWM Channels with Programmable Resolution from 2 to 16 Bits
– Output Compare Modulator
– 8-channel, 10-bit ADC
8 Single-ended Channels
7 Differential Channels
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
– Byte-oriented Two-wire Serial Interface
– Dual Programmable Serial USARTs
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with On-chip Oscillator
– On-chip Analog Comparator
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and
Extended Standby
– Software Selectable Clock Frequency
– ATmega103 Compatibility Mode Selected by a Fuse
– Global Pull-up Disable
I/O and Packages
– 53 Programmable I/O Lines
– 64-lead TQFP and 64-pad QFN/MLF
Operating Voltages
– 2.7 - 5.5V ATmega128L
– 4.5 - 5.5V ATmega128
Speed Grades
– 0 - 8MHz ATmega128L
– 0 - 16MHz ATmega128
®
®
AVR
8-bit Microcontroller
(1)
8-bit
Microcontroller
with 128KBytes
In-System
Programmable
Flash
ATmega128
ATmega128L
Rev. 2467V–AVR–02/11

ATMEGA128RFA1-ZU Summary of contents

  • Page 1

    ... Features • High-performance, Low-power Atmel • Advanced RISC Architecture – 133 Powerful Instructions – Most Single Clock Cycle Execution – General Purpose Working Registers + Peripheral Control Registers – Fully Static Operation – 16MIPS Throughput at 16MHz – On-chip 2-cycle Multiplier • High Endurance Non-volatile Memory segments – ...

  • Page 2

    ... PB3 (OC0) PB4 (OC1A) PB5 (OC1B) PB6 Note: Overview The Atmel enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega128 achieves throughputs approaching 1MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. ATmega128 2 ...

  • Page 3

    Block Diagram Figure 2. Block Diagram PF0 - PF7 VCC GND PORTF DRIVERS DATA REGISTER PORTF REG. PORTF AVCC ADC AGND AREF PROGRAM JTAG TAP COUNTER PROGRAM ON-CHIP DEBUG FLASH BOUNDARY- INSTRUCTION SCAN REGISTER PROGRAMMING PEN INSTRUCTION LOGIC DECODER CONTROL ...

  • Page 4

    ... Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega128 is a powerful microcontroller that provides a highly flexible and cost effec- tive solution to many embedded control applications. The ATmega128 device is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits ...

  • Page 5

    ... ATmega103 By programming the M103C fuse, the Atmel Compatibility Mode ATmega103 regards to RAM, I/O pins and interrupt vectors as described above. However, some new features in ATmega128 are not available in this compatibility mode, these features are listed below: • One USART instead of two, Asynchronous mode only. Only the eight least significant bits of the Baud Rate Register is available. • ...

  • Page 6

    ... The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the Atmel page 76. In ATmega103 compatibility mode, Port C is output only, and the port C pins are not tri- stated when a reset condition becomes active ...

  • Page 7

    RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in 50. Shorter pulses are not guaranteed ...

  • Page 8

    ... Resources A comprehensive set of development tools, application notes, and datasheets are available for download on http://www.atmel.com/avr. Note: Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C ...

  • Page 9

    ... AVR CPU Core Introduction This section discusses the Atmel CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals and handle interrupts. Architectural Figure 3. Block Diagram of the AVR Architecture Overview In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data ...

  • Page 10

    Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word for- mat. Every program memory address contains a 16-bit or 32-bit instruction. ...

  • Page 11

    Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter- rupt enable control is then performed in separate control registers. If the Global Interrupt Enable ...

  • Page 12

    Figure 4. AVR CPU General Purpose Working Registers Most of the instructions operating on the Register file have direct access to all registers, and most of them are single cycle instructions. As shown in directly into the first 32 locations ...

  • Page 13

    Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the ...

  • Page 14

    Figure 6 vard architecture and the fast-access Register file concept. This is the basic pipelining concept to obtain MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. ...

  • Page 15

    There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these interrupts, the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling ...

  • Page 16

    When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. Assembly Code Example sei sleep; enter sleep, waiting for interrupt ; note: will enter sleep ...

  • Page 17

    ... AVR This section describes the different memories in the Atmel tecture has two main memory spaces, the Data Memory and the Program Memory space. In ATmega128 addition, the ATmega128 features an EEPROM Memory for data storage. All three memory Memories spaces are linear and regular. ...

  • Page 18

    ... SRAM Data The Atmel Memory as listed in Table 1. Memory Configurations Configuration Normal mode ATmega103 Compatibility mode Figure 9 The ATmega128 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used ...

  • Page 19

    The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented ...

  • Page 20

    ... SRAM access is performed in two clk Figure 10. On-chip Data SRAM Access Cycles EEPROM Data The Atmel separate data space, in which single bytes can be read and written. The EEPROM has an Memory endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...

  • Page 21

    Bits 11..0 – EEAR11..0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL – specify the EEPROM address in the 4 Kbytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value ...

  • Page 22

    The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a ...

  • Page 23

    The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (for example, by disabling inter- rupts globally) so that no interrupts will occur during execution of these ...

  • Page 24

    The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ; Wait for completion ...

  • Page 25

    ... I/O Memory The I/O space definition of the ATmega128 is shown in All Atmel may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions ...

  • Page 26

    Figure 11. External Memory with Sector Select External Memory Note: ATmega103 Both External Memory Control Registers (XMCRA and XMCRB) are placed in Extended I/O Compatibility space. In ATmega103 compatibility mode, these registers are not available, and the features selected by ...

  • Page 27

    The control bits for the External Memory Interface are located in three registers, the MCU Con- trol Register – MCUCR, the External Memory Control Register A – XMCRA, and the External Memory Control Register B – XMCRB. When the XMEM ...

  • Page 28

    Pull-up and Bus- The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to keeper one. To reduce power consumption in sleep mode recommended to disable the pull-ups by writing the Port ...

  • Page 29

    Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1 System Clock (CLK Note: Figure 15. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0 System Clock (CLK Note: 2467V–AVR–02/ CPU ...

  • Page 30

    Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1 System Clock (CLK DA7:0 (XMBK = 0) DA7:0 (XMBK = 1) Note: XMEM Register Description MCU Control Register – MCUCR Bit Read/Write Initial Value • Bit ...

  • Page 31

    Bit 6..4 – SRL2, SRL1, SRL0: Wait-state Sector Limit It is possible to configure different wait-states for different External Memory addresses. The external memory address space can be divided in two sectors that have separate wait-state bits. The SRL2, ...

  • Page 32

    External Memory Control Register B – Bit XMCRB Read/Write Initial Value • Bit 7– XMBK: External Memory Bus-keeper Enable Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper is enabled, it will ensure ...

  • Page 33

    To the Application software, the external 32 Kbyte memory will appear as one linear 32 Kbyte address space from 0x1000 to 0x8FFF. Figure 17. Address Map with 32 Kbyte External Memory 2467V–AVR–02/11 Memory Configuration A AVR ...

  • Page 34

    Using all 64 Kbyte Since the External Memory is mapped after the Internal Memory as shown in Locations of External Kbyte of External Memory is available by default (address space 0x0000 to 0x10FF is reserved Memory for internal memory). However, ...

  • Page 35

    System Clock and Clock Options Clock Systems Figure 18 need not be active at a given time. In order to reduce power consumption, the clocks to modules and their not being used can be halted by using different sleep modes, ...

  • Page 36

    Asynchronous Timer The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly Clock – clk from an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Coun- ASY ter as a real-time counter even when the ...

  • Page 37

    Note: The various choices for each clocking option is given in the following sections. When the CPU wakes up from Power-down or Power-save, the selected clock source is used to time the start- up, ensuring stable Oscillator operation before instruction ...

  • Page 38

    Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be con- figured for use as an On-chip Oscillator, as shown in ceramic resonator may be used. The CKOPT fuse selects between two different ...

  • Page 39

    Table 9. Start-up Times for the Crystal Oscillator Clock Selection CKSEL0 Notes: Low-frequency To use a 32.768kHz watch crystal as the clock source for the device, the Low-frequency Crystal Oscillator must be ...

  • Page 40

    External RC For timing insensitive applications, the External RC configuration shown in Oscillator used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22pF. By programming the CKOPT fuse, the user can enable ...

  • Page 41

    ... RC Oscillator. At 5V, 25°C and 1.0MHz Oscillator frequency selected, this calibration gives a frequency within ±3% of the nominal frequency. Using calibration methods as described in application notes available at www.atmel.com/avr it is possible to achieve ±1% accuracy at any given V used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out ...

  • Page 42

    The calibrated Oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or ...

  • Page 43

    Timer/Counter For AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), the crystal is Oscillator connected directly between the pins. No external capacitors are needed. The Oscillator is opti- mized for use with a 32.768kHz watch crystal. Applying an external ...

  • Page 44

    Power Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- Management tion to the application’s requirements. and Sleep To ...

  • Page 45

    Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue ...

  • Page 46

    Standby Mode When the SM2..0 bits are 110 and an External Crystal/Resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. ...

  • Page 47

    Minimizing Power There are several issues to consider when trying to minimize the power consumption in an AVR Consumption controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so ...

  • Page 48

    JTAG Interface and If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down or On-chip Debug Power save sleep mode, the main clock source remains enabled. In these sleep modes, this will System ...

  • Page 49

    ... This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the CKSEL fuses. The different selec- tions for the delay period are presented in Reset Sources The Atmel • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • ...

  • Page 50

    Figure 22. Reset Logic Table 19. Reset Characteristics Symbol V POT V RST t RST V BOT t BOD V HYST Notes: ATmega128 PEN L Q Pull-up Resistor Power-On Reset Circuit Brown-Out BODEN Reset Circuit BODLEVEL Pull-up ...

  • Page 51

    Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage. ...

  • Page 52

    Figure 25. External Reset During Operation Brown-out Detection ATmega128 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V ing operation by comparing fixed trigger level. The trigger level for the BOD can be selected by ...

  • Page 53

    ... Bit Read/Write Initial Value Note that only EXTRF and PORF are available in Atmel • Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset writing a logic zero to the flag. • ...

  • Page 54

    Voltage Reference The voltage reference has a start-up time that may influence the way it should be used. The Enable Signals and start-up time is given in Start-up Time erence is on during the following situations: 1. When the BOD ...

  • Page 55

    Table 21. WDT Configuration as a Function of the Fuse Settings of M103C and WDTON. M103C Unprogrammed Unprogrammed Programmed Programmed Figure 28. Watchdog Timer Watchdog Timer Control Register – Bit WDTCR Read/Write Initial Value • Bits 7..5 – Res: Reserved ...

  • Page 56

    In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, ...

  • Page 57

    The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Assembly ...

  • Page 58

    In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence. 2. Within the next four clock cycles, in ...

  • Page 59

    ... Interrupts This section describes the specifics of the interrupt handling as performed in Atmel ATmega128. For a general explanation of the AVR interrupt handling, refer to rupt Handling” on page Interrupt Vectors in ATmega128 Table 23. Reset and Interrupt Vectors Vector No 2467V–AVR–02/11 14. Program (2) Address Source Interrupt Definition ...

  • Page 60

    Table 23. Reset and Interrupt Vectors Vector No Notes: Table 24 BOOTRST and IVSEL settings. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be ...

  • Page 61

    The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega128 is: Address LabelsCode $0000 $0002 $0004 $0006 $0008 $000A $000C $000E $0010 $0012 $0014 $0016 $0018 $001A $001C $001E $0020 $0022 $0024 $0026 $0028 ...

  • Page 62

    When the BOOTRST fuse is unprogrammed, the Boot section size set to 8Kbytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt ...

  • Page 63

    Moving Interrupts The General Interrupt Control Register controls the placement of the interrupt vector table. Between Application and Boot Space MCU Control Register – MCUCR Bit Read/Write Initial Value • Bit 1 – IVSEL: Interrupt Vector Select ...

  • Page 64

    Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is ...

  • Page 65

    ... I/O Ports Introduction All Atmel I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input) ...

  • Page 66

    Ports as General The ports are bi-directional I/O ports with optional internal pull-ups. Digital I/O description of one I/O port pin, here generically called Pxn. Figure 30. General Digital I/O Pxn Note: Configuring the Pin Each port pin consists of ...

  • Page 67

    PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept- able high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the ...

  • Page 68

    LATCH” signal. The signal value is latched when the system clock goes low clocked into the PINxn Register at the succeeding positive clock edge. As indi- cated by the two arrows t between ...

  • Page 69

    The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned to port pins 6 and 7. The ...

  • Page 70

    Unconnected pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ing inputs should ...

  • Page 71

    Table 26 ure 33 the modules having the alternate function. Table 26. Generic Description of Overriding Signals for Alternate Functions. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO The following subsections shortly describes the alternate functions ...

  • Page 72

    Special Function IO Register – SFIOR Bit Read/Write Initial Value • Bit 2 – PUD: Pull-up disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are ...

  • Page 73

    Table 29. Overriding Signals for Alternate Functions in PA3..PA0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Alternate Functions of The Port B pins with alternate functions are shown in Port B Table 30. Port B ...

  • Page 74

    OC1B, Bit 6 OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this ...

  • Page 75

    Table 31. Overriding Signals for Alternate Functions in PB7..PB4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: Table 32. Overriding Signals for Alternate Functions in PB3..PB0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE ...

  • Page 76

    Alternate Functions of In ATmega103 compatibility mode, Port C is output only. The ATmega128 is by default shipped Port C in compatibility mode. Thus, if the parts are not programmed before they are put on the PCB, PORTC will be ...

  • Page 77

    Table 35. Overriding Signals for Alternate Functions in PC3..PC0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: Alternate Functions of The Port D pins with alternate functions are shown in Port D Table 36. Port ...

  • Page 78

    ICP1 – Port D, Bit 4 ICP1 – Input Capture Pin1: The PD4 pin can act as an Input Capture Pin for Timer/Counter1. • INT3/TXD1 – Port D, Bit 3 INT3, External Interrupt source 3: The PD3 pin can ...

  • Page 79

    Table 37. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 38. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI ...

  • Page 80

    Alternate Functions of The Port E pins with alternate functions are shown in Port E Table 39. Port E Pins Alternate Functions Port Pin PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Note: • INT7/ICP3 – Port E, Bit 7 ...

  • Page 81

    XCK0, USART0 External clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK0 pin is active only when the USART0 operates in Synchronous mode. • PDO/TXD0 – Port E, Bit ...

  • Page 82

    Table 41. Overriding Signals for Alternate Functions in PE3..PE0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Alternate Functions of The Port F has an alternate function as analog input for the ADC as shown in ...

  • Page 83

    TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin. • TCK, ADC4 – Port F, Bit 4 ...

  • Page 84

    ... Alternate Functions of In Atmel Port G Port G, and Port G cannot be used as General Digital Port Pins. The alternate pin configuration is as follows: Table 45. Port G Pins Alternate Functions Port Pin PG4 PG3 PG2 PG1 PG0 • TOSC1 – Port G, Bit 4 TOSC1, Timer Oscillator pin 1: When the AS0 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter0, pin PG4 is disconnected from the port, and becomes the input of the inverting Oscillator amplifier ...

  • Page 85

    Table 47. Overriding Signals for Alternate Functions in PG0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 2467V–AVR–02/11 ATmega128 PG0/WR SRE 0 SRE 1 SRE – – 85 ...

  • Page 86

    Register Description for I/O Ports Port A Data Register – Bit PORTA Read/Write Initial Value Port A Data Direction Bit Register – DDRA Read/Write Initial Value Port A Input Pins Bit Address – PINA Read/Write Initial Value Port B Data ...

  • Page 87

    ... Address – PINC Read/Write Initial Value In Atmel being Push-Pull Zero Output. The port pins assumes their initial value, even if the clock is not running. Note that the DDRC and PINC Registers are available in ATmega103 compatibility mode, and should not be used for 100% back-ward compatibility. ...

  • Page 88

    ... Read/Write Initial Value Port F Input Pins Bit Address – PINF Read/Write Initial Value Note that PORTF and DDRF Registers are not available in Atmel ity mode where Port F serves as digital input only. Port G Data Register – Bit PORTG Read/Write Initial Value Port G Data Direction Bit Register – ...

  • Page 89

    ... EICRA Read/Write Initial Value This Register can not be reached in Atmel value defines INT3:0 as low level interrupts ATmega103. • Bits 7..0 – ISC31, ISC30 – ISC00, ISC00: External Interrupt Sense Control Bits The External Interrupts are activated by the external pins INT3:0 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set ...

  • Page 90

    Table 48. Interrupt Sense Control ISCn1 Note: Table 49. Asynchronous External Interrupt Characteristics Symbol t INT External Interrupt Control Register B – Bit EICRB Read/Write Initial Value • Bits 7..0 – ISC71, ISC70 - ISC41, ISC40: ...

  • Page 91

    External Interrupt Mask Register – Bit EIMSK Read/Write Initial Value • Bits 7..0 – INT7 – INT0: External Interrupt Request Enable When an INT7 – INT0 bit is written to one and the I-bit in the Status ...

  • Page 92

    Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: Timer/Counter0 • Single Channel Counter with PWM and • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) Asynchronous ...

  • Page 93

    The output from the clock select logic is referred to as the timer clock (clk The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter value at all times. The result ...

  • Page 94

    Signal description (internal signals): count direction clear clk T0 top bottom Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the clock select bits (CS02:0). When no clock ...

  • Page 95

    Figure 36. Output Compare Unit, Block Diagram The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff- ering is ...

  • Page 96

    The OC0 Register keeps its value even when changing between waveform generation modes. Be aware that the COM01:0 bits are not double buffered together with the compare value. Changing the COM01:0 bits will take ...

  • Page 97

    Modes of The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is Operation defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output mode (COM01:0) bits. The Compare Output mode bits ...

  • Page 98

    TCNT0, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. For generating a waveform output in ...

  • Page 99

    Figure 39. Fast PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter overflow flag ( is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of ...

  • Page 100

    Phase Correct PWM The phase correct PWM mode (WGM01 provides a high resolution phase correct PWM Mode waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to ...

  • Page 101

    PWM frequency for the output when using phase correct PWM can be calculated by the follow- ing equation: The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR0 Register ...

  • Page 102

    Figure 42. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 43 Figure 43. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (f clk clk (clk TCNTn OCRn OCFn Figure 44 ATmega128 102 I/O Tn /8) I/O ...

  • Page 103

    Figure 44. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Pres- caler (f clk_I/O clk clk (clk TCNTn (CTC) OCRn OCFn 8-bit Timer/Counter Register Description Timer/Counter Control Register – TCCR0 Bit Read/Write Initial Value • Bit 7 – ...

  • Page 104

    Table 52. Waveform Generation Mode Bit Description Mode Note: • Bit 5:4 – COM01:0: Compare Match Output Mode These bits control the output compare pin (OC0) behavior. If one or both of the COM01:0 bits are ...

  • Page 105

    Table 55. Compare Output Mode, Phase Correct PWM Mode COM01 Note: • Bit 2:0 – CS02:0: Clock Select The three clock select bits select the clock source to be used by the Timer/Counter, see 56. Table ...

  • Page 106

    Asynchronous Operation of the Timer/Counter Asynchronous Status Register – ASSR Bit Read/Write Initial Value • Bit 3 – AS0: Asynchronous Timer/Counter0 When AS0 is written to zero, Timer/Counter0 is clocked from the I/O clock, clk written to one, Timer/Counter is ...

  • Page 107

    When writing to one of the registers TCNT0, OCR0, or TCCR0, the value is transferred to a temporary register, and latched after two positive edges on TOSC1. The user should not write a new value before the contents of ...

  • Page 108

    During asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing ...

  • Page 109

    Timer/Counter Figure 45. Prescaler for Timer/Counter0 Prescaler clk TOSC1 PSR0 CS00 CS01 CS02 The clock source for Timer/Counter0 is named clk system clock clk from the TOSC1 pin. This enables use of Timer/Counter0 as a Real Time Counter (RTC). When ...

  • Page 110

    ATmega128 110 • Bit 1 – PSR0: Prescaler Reset Timer/Counter0 When this bit is one, the Timer/Counter0 prescaler will be reset. This bit is normally cleared immediately by hardware. If this bit is written when Timer/Counter0 is operating in asynchronous ...

  • Page 111

    ... Ten Independent Interrupt Sources (TOV1, OCF1A, OCF1B, OCF1C, ICF1, TOV3, OCF3A, OCF3B, OCF3C, and ICF3) Restrictions in Note that in Atmel ATmega103 available (Timer/Counter1). Also note that in ATmega103 compatibility mode, the Compatibility Mode Timer/Counter1 has two Compare Registers (Compare A and Compare B) only. ...

  • Page 112

    Figure 46. 16-bit Timer/Counter Block Diagram Note: Registers The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Reg- ister (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are described ...

  • Page 113

    See “Output Compare Units” on page match flag (OCFnA/B/C) which can be used to generate an output compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the ...

  • Page 114

    Accessing 16-bit The TCNTn, OCRnA/B/C, and ICRn are 16-bit registers that can be accessed by the AVR CPU Registers via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write opera- tions. Each 16-bit ...

  • Page 115

    The following code examples show how atomic read of the TCNTn Register contents. Reading any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_ReadTCNTn: C Code Example unsigned ...

  • Page 116

    The following code examples show how atomic write of the TCNTn Register contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNTn: ; Save global interrupt ...

  • Page 117

    Timer/Counter The Timer/Counter can be clocked by an internal or an external clock source. The clock source Clock Sources is selected by the clock select logic which is controlled by the Clock Select (CSn2:0) bits located in the Timer/Counter Control ...

  • Page 118

    OCnx. For more details about advanced counting sequences and waveform generation, see The Timer/Counter Overflow (TOVn) flag is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be ...

  • Page 119

    Temporary Register (TEMP). When the CPU reads the ICRnH I/O location it will access the TEMP Register. The ICRn Register can only be written when using a Waveform Generation mode that utilizes the ICRn Register for ...

  • Page 120

    Output Compare The 16-bit comparator continuously compares TCNTn with the Output Compare Register Units (OCRnx). If TCNT equals OCRnx the comparator signals a match. A match will set the Output Compare Flag (OCFnx) at the next timer clock cycle. If ...

  • Page 121

    The OCRnx Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCRnx buffer register, and if double buffering is disabled the CPU will access the OCRnx directly. ...

  • Page 122

    Compare Match The Compare Output mode (COMnx1:0) bits have two functions. The waveform generator uses Output Unit the COMnx1:0 bits for defining the output compare (OCnx) state at the next compare match. Secondly the COMnx1:0 bits control the OCnx pin ...

  • Page 123

    Modes of The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is Operation defined by the combination of the Waveform Generation mode (WGMn3:0) and Compare Output mode (COMnx1:0) bits. The Compare Output mode bits ...

  • Page 124

    An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn flag according to the register used to define the TOP value. If the inter- rupt is enabled, the ...

  • Page 125

    Figure 52. Fast PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addition the OCnA or ICFn flag is set at the same timer clock cycle as ...

  • Page 126

    The PWM frequency for the output can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM ...

  • Page 127

    Figure 53. Phase Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. When either OCRnA or ICRn is used for defining the TOP value, the OCnA or ...

  • Page 128

    The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx ...

  • Page 129

    Figure 54. Phase and Frequency Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at BOTTOM). ...

  • Page 130

    The extreme values for the OCRnx Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal ...

  • Page 131

    Figure 57 frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that ...

  • Page 132

    Timer/Counter Register Description Timer/Counter1 Control Register A – Bit TCCR1A Read/Write Initial Value Timer/Counter3 Control Register A – Bit TCCR3A Read/Write Initial Value • Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A • Bit 5:4 – COMnB1:0: ...

  • Page 133

    Table 59 mode Table 59. Compare Output Mode, Fast PWM COMnA1/COMnB1/ COMnC1 Note: Table 59 rect and frequency correct PWM mode. Table 60. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM COMnA1/COMnB1/ COMnC1 Note: 2467V–AVR–02/11 shows the ...

  • Page 134

    Bit 1:0 – WGMn1:0: Waveform Generation Mode Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of wave- form ...

  • Page 135

    Timer/Counter1 Control Register B – Bit TCCR1B Read/Write Initial Value Timer/Counter3 Control Register B – Bit TCCR3B Read/Write Initial Value • Bit 7 – ICNCn: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. ...

  • Page 136

    Table 62. Clock Select Bit Description CSn2 external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the counter even if the pin is configured as ...

  • Page 137

    Timer/Counter1 – TCNT1H and TCNT1L Bit Read/Write Initial Value Timer/Counter3 – TCNT3H and TCNT3L Bit Read/Write Initial Value The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct access, both for read and for write operations, to the ...

  • Page 138

    Output Compare Register 3 B – Bit OCR3BH and OCR3BL Read/Write Initial Value Output Compare Register 3 C – Bit OCR3CH and OCR3CL Read/Write Initial Value The Output Compare Registers contain a 16-bit value that is continuously compared with the ...

  • Page 139

    Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding interrupt vector ...

  • Page 140

    Bit 2 – TOIE3: Timer/Counter3, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Overflow Interrupt is enabled. The corresponding interrupt vector (See “Interrupts” ...

  • Page 141

    TOV1 is automatically cleared when the Timer/Counter1 Overflow interrupt vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. Extended Timer/Counter Bit Interrupt Flag Register – ETIFR Read/Write Initial Value • Bit 7:6 ...

  • Page 142

    Note that a forced output compare (FOC1C) strobe will not set the OCF1C flag. OCF1C is automatically cleared when the Output Compare Match 1 C interrupt vector is exe- cuted. Alternatively, OCF1C can be cleared by writing a logic one ...

  • Page 143

    Timer/Counter3, Timer/Counter3, Timer/Counter1, and Timer/Counter2 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to all of Timer/Counter2, the mentioned Timer/Counters. and Timer/Counter1 Prescalers Internal Clock Source The Timer/Counter can be clocked ...

  • Page 144

    Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the sys- tem clock frequency (f sampling, the maximum ...

  • Page 145

    Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: Timer/Counter2 • Single Channel Counter with PWM • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse width Modulator (PWM) • Frequency ...

  • Page 146

    The double buffered Output Compare Register (OCR2) is compared with the Timer/Counter value at all times. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare ...

  • Page 147

    Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the clock select bits (CS22:0). When no clock source is selected (CS22 the timer is stopped. ...

  • Page 148

    The double buffering synchronizes the update of the OCR2 Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR2 ...

  • Page 149

    Figure 64. Compare Match Output Unit, Schematic The general I/O port function is overridden by the output compare (OC2) from the waveform generator if either of the COM21:0 bits are set. However, the OC2 pin direction (input or output) is ...

  • Page 150

    In normal operation the Timer/Counter overflow flag ( timer clock cycle as the TCNT2 becomes zero. The bit, except that it ...

  • Page 151

    The N variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the normal mode of operation, the TOV2 flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. Fast ...

  • Page 152

    The PWM frequency for the output can be calculated by the following equation: The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR2 Register represents special cases when generating a PWM ...

  • Page 153

    Figure 67. Phase Correct PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The interrupt flag can be used to generate an interrupt each time the counter reaches ...

  • Page 154

    The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. Timer/Counter The Timer/Counter is a ...

  • Page 155

    Figure 70. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (f clk clk (clk TCNTn OCRn OCFn Figure 71 Figure 71. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Pres- caler (f clk_I/O clk clk (clk TCNTn (CTC) ...

  • Page 156

    Timer/Counter Register Description Timer/Counter Control Register – TCCR2 Bit Read/Write Initial Value • Bit 7 – FOC2: Force Output Compare The FOC2 bit is only active when the WGM20 bit specifies a non-PWM mode. However, for ensuring compatibility with ...

  • Page 157

    Table 65. Compare Output Mode, Non-PWM Mode COM21 Table 66 mode. Table 66. Compare Output Mode, Fast PWM Mode COM21 Note: Table 67 PWM mode. Table 67. Compare Output Mode, Phase Correct ...

  • Page 158

    Table 68. Clock Select Bit Description CS22 external pin modes are used for the Timer/Counter2, transitions on the T2 pin will clock the counter even if the pin is configured as an output. This feature ...

  • Page 159

    Timer/Counter Interrupt Flag Register Bit – TIFR Read/Write Initial Value • Bit 7 – OCF2: Output Compare Flag 2 The OCF2 bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2 – Output ...

  • Page 160

    Output Compare Modulator (OCM1C2) Overview The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit Timer/Counter1 and the Output Compare Unit of ...

  • Page 161

    When the modulator is enabled the type of modulation (logical AND or OR) can be selected by the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the COMnx1:0 bit setting. Timing Example Figure 74 ...

  • Page 162

    ... Serial The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the Atmel AVR ATmega128 and peripheral devices or between several AVR devices. The Peripheral ATmega128 SPI includes the following features: Interface – SPI • Full-duplex, Three-wire Synchronous Data Transfer • ...

  • Page 163

    When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts ...

  • Page 164

    Note: The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual data direction register controlling the SPI pins. DD_MOSI, DD_MISO ...

  • Page 165

    The following code examples show how to initialize the SPI as a slave and how to perform a sim- ple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 2467V–AVR–02/11 (1) ...

  • Page 166

    SS Pin Functionality Slave Mode When the SPI is configured as a slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the ...

  • Page 167

    SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas- ter mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. ...

  • Page 168

    SPI Status Register – SPSR Bit Read/Write Initial Value • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in SPCR is set and global ...

  • Page 169

    Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in 77 and ensuring sufficient time for data ...

  • Page 170

    USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or ...

  • Page 171

    Figure 79. USART Block Diagram Note: The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter, and Receiver. Control registers are shared by all units. The clock generation ...

  • Page 172

    AVR USART vs. AVR The USART is fully compatible with the AVR UART regarding: UART – Compatibility • Bit locations inside all USART registers • Baud Rate Generation • Transmitter Operation • Transmit Buffer Functionality • Receiver Operation However, the ...

  • Page 173

    Internal Clock Internal clock generation is used for the asynchronous and the synchronous master modes of Generation – The operation. The description in this section refers to Baud Rate Generator The USART Baud Rate Register ...

  • Page 174

    External Clock External clocking is used by the synchronous slave modes of operation. The description in this section refers to External clock input from the XCK pin is sampled by a synchronization register to minimize the chance of meta-stability. The ...

  • Page 175

    Frame Formats A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid ...

  • Page 176

    USART The USART has to be initialized before any communication can take place. The initialization pro- Initialization cess normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. For ...

  • Page 177

    Data Transmission The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB – The USART Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overrid- den by the USART ...

  • Page 178

    Sending Frames with If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB 9 Data Bit before the low byte of the character is written to UDR. The following code ...

  • Page 179

    Interrupt routine must either write new data to UDR in order to clear UDRE or disable the data register empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The ...

  • Page 180

    ATmega128 180 The following code example shows a simple USART receive function based on polling of the Receive Complete (RXC) flag. When using frames with less than eight bits the most significant bits of the data read from the UDR ...

  • Page 181

    Receiving Frames with If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB 9 Data Bits before reading the low bits from the UDR. This rule applies to the FE, DOR and ...

  • Page 182

    Note: Receive Compete Flag The USART Receiver has one flag that indicates the receiver state. and Interrupt The Receive Complete (RXC) flag indicates if there are unread data present in the receive buf- fer. This flag is one when unread ...

  • Page 183

    Parity Checker The parity checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the parity checker calculates the ...

  • Page 184

    Asynchronous Clock The clock recovery logic synchronizes internal clock to the incoming serial frames. Recovery illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for normal mode, and ...

  • Page 185

    Figure 85. Stop Bit Sampling and Next Start Bit Sampling RxD Sample (U2X = 0) Sample (U2X = 1) The same majority voting is done to the stop bit as done for the other bits in the frame. If the ...

  • Page 186

    Table 75. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = 0) # (Data+Parity Bit) Table 76. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2X = 1) # (Data+Parity Bit) The recommendations of the ...

  • Page 187

    The Multi-processor Communication mode enables several slave MCUs to receive data from a master MCU. This is done by first decoding an address frame to find out which MCU has been addressed particular slave MCU has been addressed, ...

  • Page 188

    USART Register Description USARTn I/O Data Register – UDRn Bit Read/Write Initial Value The USARTn Transmit Data Buffer Register and USARTn Receive Data Buffer Registers share the same I/O address referred to as USARTn Data Register or UDRn. The Transmit ...

  • Page 189

    This bit is set if the next character in the receive buffer had a Frame Error when received. I.e. when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the ...

  • Page 190

    Writing this bit to one enables the USARTn Transmitter. The Transmitter will override normal port operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to zero) will not become effective until ongoing and pending transmissions ...

  • Page 191

    Bit 3 – USBSn: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 79. USBSn Bit Settings • Bit 2:1 – UCSZn1:0: Character Size The ...

  • Page 192

    Bit 15:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRnH is written. • Bit 11:0 – UBRRn11:0: USARTn Baud Rate Register This is ...

  • Page 193

    Examples of Baud For standard crystal and resonator frequencies, the most commonly used baud rates for asyn- Rate Setting chronous operation can be generated by using the UBRR settings in which yield an actual baud rate differing less than 0.5% ...

  • Page 194

    Table 83. Examples of UBRR Settings for Commonly Used Oscillator Frequencies f = 3.6864MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% 47 14.4k ...

  • Page 195

    Table 84. Examples of UBRR Settings for Commonly Used Oscillator Frequencies f = 8.0000MHz osc Baud U2X = 0 Rate (bps) UBRR Error UBRR 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% 103 14.4k 34 -0.8% 68 ...

  • Page 196

    Table 85. Examples of UBRR Settings for Commonly Used Oscillator Frequencies Baud U2X = 0 Rate (bps) UBRR 2400 416 4800 207 9600 103 14.4k 68 19.2k 51 28.8k 34 38.4k 25 57.6k 16 76.8k 12 115.2k 8 230.4k 3 ...

  • Page 197

    Two-wire Serial Interface Features • Simple yet Powerful and Flexible Communication Interface, only Two Bus Lines Needed • Both Master and Slave Operation Supported • Device can Operate as Transmitter or Receiver • 7-bit Address Space allows up to 128 ...

  • Page 198

    Note that all AVR devices connected to the TWI bus must be powered in order to allow any bus operation. The number of devices that can be connected to the bus is only limited by the bus capacitance limit ...

  • Page 199

    Address Packet All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one Format READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read opera- tion is to ...

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    Figure 90. Data Packet Format Aggregate SDA SDA from Transmitter SDA from Receiver SCL from Master Combining Address A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and Data Packets Into and a STOP ...