ATmega1284RZAP

Manufacturer Part NumberATmega1284RZAP
ManufacturerAtmel Corporation
ATmega1284RZAP datasheets
 

Specifications of ATmega1284RZAP

Flash (kbytes)128 KbytesMax. Operating Frequency20 MHz
Max I/o Pins32Spi3
Twi (i2c)1Uart2
Adc Channels8Adc Resolution (bits)10
Adc Speed (ksps)15Analog Comparators1
Crypto EngineNoSram (kbytes)16
Eeprom (bytes)4096Operating Voltage (vcc)1.8 to 3.6
Timers3Frequency Band2.4 GHz
Max Data Rate (mb/s)0.25Antenna DiversityNo
External Pa ControlNoPower Output (dbm)3
Receiver Sensitivity (dbm)-101Receive Current Consumption (ma)16.0
Transmit Current Consumption (ma)17.0Link Budget (dbm)104
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Features
High-performance, Low-power AVR
Advanced RISC Architecture
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– On-chip 2-cycle Multiplier
Nonvolatile Program and Data Memories
– 128K Bytes of In-System Self-Programmable Flash
Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– 4K Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– 16K Bytes Internal SRAM
– Programming Lock for Software Security
JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– Two 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel, 10-bit ADC
Differential mode with selectable gain at 1x, 10x or 200x
– Byte-oriented Two-wire Serial Interface
– Two Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
and Extended Standby
I/O and Packages
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF
Operating Voltages
– 1.8 - 5.5V for ATmega1284P
Speed Grades
– 0 - 4 MHz @ 1.8 - 5.5V
– 0 - 10 MHz @ 2.7 - 5.5V
– 0 - 20 MHz @ 4.5 - 5.5V
Power Consumption at 1 MHz, 1.8V, 25°C
– Active: 0.4 mA
– Power-down Mode: 0.1 µA
– Power-save Mode: 0.7 µA (Including 32 kHz RTC)
®
8-bit Microcontroller
8-bit
Microcontroller
with 128K Bytes
In-System
Programmable
Flash
ATmega1284P
Preliminary
8059D–AVR–11/09

ATmega1284RZAP Summary of contents

  • Page 1

    Features • High-performance, Low-power AVR • Advanced RISC Architecture – 131 Powerful Instructions – Most Single-clock Cycle Execution – General Purpose Working Registers – Fully Static Operation – MIPS Throughput at 20 MHz – ...

  • Page 2

    Pin Configurations Figure 1-1. Note: 8059D–AVR–11/09 Pinout ATmega1284P (PCINT8/XCK0/T0) PB0 (PCINT9/CLKO/T1) PB1 (PCINT10/INT2/AIN0) PB2 (PCINT11/OC0A/AIN1) PB3 (PCINT12/OC0B/SS) PB4 (PCINT13/ICP3/MOSI) PB5 (PCINT14/OC3A/MISO) PB6 (PCINT15/OC3B/SCK) PB7 RESET VCC GND XTAL2 XTAL1 (PCINT24/RXD0/T3) PD0 (PCINT25/TXD0) PD1 (PCINT26/RXD1/INT0) PD2 (PCINT27/TXD1/INT1) PD3 (PCINT28/XCK1/OC1B) PD4 ...

  • Page 3

    Overview The ATmega1284P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega1284P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to ...

  • Page 4

    I/O lines, 32 general purpose working registers, Real Time Counter (RTC), three flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented 2-wire Serial Inter- face, a 8-channel, 10-bit ADC with optional differential input stage with programmable ...

  • Page 5

    Port B (PB7:PB0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B ...

  • Page 6

    Resources A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr. 4. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware ...

  • Page 7

    AVR CPU Core 5.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control ...

  • Page 8

    ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three ...

  • Page 9

    Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and ...

  • Page 10

    General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output ...

  • Page 11

    The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and ...

  • Page 12

    SPH and SPL – Stack Pointer High and Stack pointer Low Bit 0x3E (0x5E) 0x3D (0x5D) Read/Write Initial Value 5.5.2 RAMPZ – Extended Z-pointer Register for ELPM/SPM Bit 0x3B (0x5B) Read/Write Initial Value For ELPM/SPM instructions, the Z-pointer is ...

  • Page 13

    Figure 5-5. 1st Instruction Execute 2nd Instruction Execute 3rd Instruction Execute Figure 5-6 operation using two register operands is executed, and the result is stored back to the destina- tion register. Figure 5-6. Register Operands Fetch ALU Operation Execute 5.7 ...

  • Page 14

    The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that ...

  • Page 15

    Assembly Code Example sei sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example __enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */ /* note: ...

  • Page 16

    AVR Memories 6.1 Overview This section describes the different memories in the ATmega1284P. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega1284P features an EEPROM Memory for data ...

  • Page 17

    Figure 6-1. 6.3 SRAM Data Memory Figure 6-2 The ATmega1284P is a complex microcontroller with more peripheral units than can be sup- ported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended ...

  • Page 18

    The 32 general purpose working registers, 64 I/O registers, 160 Extended I/O Registers and the 16K bytes of internal data SRAM in the ATmega1284P are all accessible through all these addressing modes. The Register File is described in 10. Figure ...

  • Page 19

    EEPROM Data Memory The ATmega1284P contains 4K bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase ...

  • Page 20

    I/O Memory The I/O space definition of the ATmega1284P is shown in All ATmega1284P I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the ...

  • Page 21

    Register Description 6.6.1 EEARH and EEARL – The EEPROM Address Register Bit 0x22 (0x42) 0x21 (0x41) Read/Write Initial Value • Bits 15:12 – Res: Reserved Bits These bits are reserved bits in the ATmega1284P and will always read as ...

  • Page 22

    While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. Table 6-1. EEPM1 • Bit 3 – EERIE: EEPROM ...

  • Page 23

    When the write access time has elapsed, the EEPE bit is cleared by hardware. The user soft- ware can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is ...

  • Page 24

    The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts glob- ally) so that no interrupts will occur during execution of these functions. ...

  • Page 25

    The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example unsigned ...

  • Page 26

    GPIOR2 – General Purpose I/O Register 2 Bit 0x2B (0x4B) Read/Write Initial Value 6.6.5 GPIOR1 – General Purpose I/O Register 1 Bit 0x2A (0x4A) Read/Write Initial Value 6.6.6 GPIOR0 – General Purpose I/O Register 0 Bit 0x1E (0x3E) Read/Write ...

  • Page 27

    System Clock and Clock Options 7.1 Clock Systems and their Distribution Figure 7-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using ...

  • Page 28

    Flash Clock – clk FLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul- taneously with the CPU clock. 7.1.4 Asynchronous Timer Clock – clk The Asynchronous Timer clock allows the Asynchronous ...

  • Page 29

    Table 7-2. Typ Time-out (V Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum Vcc. The delay will not monitor the actual ...

  • Page 30

    Low Power Crystal Oscillator This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 out- put. It gives the lowest power consumption, but is not capable of driving other clock inputs, and may be ...

  • Page 31

    Table 7-4. Oscillator Source / Power Conditions Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power Notes: 7.4 Full Swing Crystal Oscillator This Crystal Oscillator is a full swing oscillator, with rail-to-rail swing on the ...

  • Page 32

    Table 7-6. Oscillator Source / Power Conditions Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power Notes: 7.5 Low Frequency Crystal Oscillator The Low-frequency Crystal ...

  • Page 33

    optional external capacitors as described the pin capacitance the load capacitance for a 32.768 kHz crystal specified by the crystal vendor the total stray ...

  • Page 34

    Calibrated Internal RC Oscillator By default, the Internal RC Oscillator provides an approximate 8 MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the the user. See 26-1 on page 326 See ”System ...

  • Page 35

    Internal Oscillator The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre- quency is nominal at 3V and 25°C. This clock may be select as the system clock by ...

  • Page 36

    Table 7-16. Power Conditions BOD enabled Fast rising power Slowly rising power When applying an external clock required to avoid sudden changes in the applied clock fre- quency to ensure stable operation of the MCU. A variation in ...

  • Page 37

    The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the ...

  • Page 38

    Register Description 7.12.1 OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write Initial Value • Bits 7:0 – CAL7:0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from ...

  • Page 39

    The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor ...

  • Page 40

    Power Management and Sleep Modes 8.1 Overview Sleep modes enable the application to shut down unused modules in the MCU, thereby saving- power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the ...

  • Page 41

    BOD Disable When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses, the BOD is actively monitoring the power supply voltage during a sleep period. To save power possible to disable the BOD by software for some ...

  • Page 42

    Power-down Mode When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power- down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the 2- wire Serial Interface, and the ...

  • Page 43

    Power Reduction Registers The Power Reduction Registers (PRR0 and PRR1), see clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read or written. Resources used ...

  • Page 44

    Watchdog Timer If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the ...

  • Page 45

    Register Description 8.12.1 SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 0x33 (0x53) Read/Write Initial Value • Bits – SM2:0: Sleep Mode Select Bits 2, 1, ...

  • Page 46

    MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 6 – BODS: BOD Sleep The BODS bit must be written to logic one in order to turn off BOD during sleep, see on page BODSE ...

  • Page 47

    Bit 5 - PRTIM0: Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. • Bit 4 - PRUSART1: Power Reduction USART1 ...

  • Page 48

    System Control and Reset 9.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP ...

  • Page 49

    Figure 9-1. BODLEVEL [2..0] 9.1.2 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined below the detection level. The POR circuit can be used to trigger the ...

  • Page 50

    Figure 9-2. TIME-OUT INTERNAL Figure 9-3. TIME-OUT INTERNAL 9.1.3 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see reset, even if the clock is not ...

  • Page 51

    Brown-out Detection ATmega1284P has an On-chip Brown-out Detection (BOD) circuit for monitoring the V during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger ...

  • Page 52

    Internal Voltage Reference ATmega1284P features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 9.2.1 Voltage Reference Enable Signals and Start-up Time ...

  • Page 53

    Watchdog Timer 9.3.1 Features • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16ms to 8s • Possible Hardware fuse Watchdog always on ...

  • Page 54

    In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four ...

  • Page 55

    Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this ...

  • Page 56

    Register Description 9.4.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 0x34 (0x54) Read/Write Initial Value • Bit 4 – JTRF: JTAG Reset Flag This bit is ...

  • Page 57

    WDTCSR – Watchdog Timer Control Register Bit (0x60) Read/Write Initial Value • Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config- ured for ...

  • Page 58

    Bit 5, 2:0 - WDP3:0: Watchdog Timer Prescaler and 0 The WDP3:0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run- ning. The different prescaling values and their corresponding time-out periods are shown ...

  • Page 59

    Interrupts 10.1 Overview This section describes the specifics of the interrupt handling as performed in ATmega1284P. For a general explanation of the AVR interrupt handling, refer to on page 10.2 Interrupt Vectors in ATmega1284P Table 10-1. Vector No. 1 ...

  • Page 60

    Table 10-1. Vector No Notes: Table 10-2 BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed ...

  • Page 61

    When the BOOTRST Fuse is unprogrammed, the Boot section ...

  • Page 62

    When the BOOTRST Fuse is programmed and the Boot section size set to 8K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code .org 0x0002 0x00002 0x00004 ...

  • Page 63

    Register Description 10.3.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the ...

  • Page 64

    Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is ...

  • Page 65

    External Interrupts 11.1 Overview The External Interrupts are triggered by the INT2:0 pin or any of the PCINT31:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT2:0 or PCINT31:0 pins are configured as outputs. This ...

  • Page 66

    If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur. Therefore, it ...

  • Page 67

    PCICR – Pin Change Interrupt Control Register Bit (0x68) Read/Write Initial Value • Bit 3 – PCIE3: Pin Change Interrupt Enable 3 When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is set ...

  • Page 68

    Bit 1 – PCIF1: Pin Change Interrupt Flag 1 When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one), ...

  • Page 69

    PCMSK0 – Pin Change Mask Register 0 Bit (0x6B) Read/Write Initial Value • Bit 7:0 – PCINT7:0: Pin Change Enable Mask 7..0 Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 ...

  • Page 70

    I/O-Ports 12.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with ...

  • Page 71

    Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 12.2 Ports as General Digital I/O The ports are bi-directional I/O ports ...

  • Page 72

    If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin ...

  • Page 73

    Figure 12-3. Synchronization when Reading an Externally Applied Pin value INSTRUCTIONS Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the ...

  • Page 74

    Assembly Code Example C Code Example unsigned char i; Note: 12.2.5 Digital Input Enable and Sleep Modes As shown in schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, ...

  • Page 75

    Unconnected Pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ing inputs ...

  • Page 76

    Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. shows how the port pin control signals from the simplified ridden by alternate functions. The overriding signals may not be present in all ...

  • Page 77

    Table 12-2 ure 12-5 in the modules having the alternate function. Table 12-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate the ...

  • Page 78

    Alternate Functions of Port A The Port A has an alternate function as the address low byte and data lines for the External Memory Interface. Table 12-3. Port Pin PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 • ADC7:0/PCINT7:0 ...

  • Page 79

    Table 12-4 on page 79 overriding signals shown in Table 12-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 12-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 8059D–AVR–11/09 and Table ...

  • Page 80

    Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 12-6. Port Pin PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 The alternate pin configuration is as follows: • SCK/OC3B/PCINT15 – Port B, ...

  • Page 81

    OC3A, Output Compare Match A output: The PB6 pin can serve as an external output for the Timer/Counter0 Output Compare. The pin has to be configured as an output (DDB6 set “one”) to serve this function. The OC3A pin is ...

  • Page 82

    CLKO, Divided System Clock: The divided system clock can be output on the PB1 pin. The divided system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTB1 and DDB1 settings. It will also be output ...

  • Page 83

    Table 12-8. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 12.3.3 Alternate Functions of Port C The Port C alternate function is as follows: Table 12-9. Port Pin PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 ...

  • Page 84

    TOSC1/PCINT22 – Port C, Bit 6 TOSC1, Timer Oscillator pin 1. The PC6 pin can serve as an external interrupt source to the MCU. PCINT22, Pin Change Interrupt source 23: The PC6 pin can serve as an external interrupt ...

  • Page 85

    Table 12-10. Overriding Signals for Alternate Functions in PC7:PC4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 12-11. Overriding Signals for Alternate Functions in PC3:PC0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV ...

  • Page 86

    Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 12-12. Port D Pins Alternate Functions Port Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 8059D–AVR–11/09 Alternate Function OC2A (Timer/Counter2 Output Compare ...

  • Page 87

    The alternate pin configuration is as follows: • OC2A/PCINT31 – Port D, Bit 7 OC2A, Output Compare Match A output: The PD7 pin can serve as an external output for the Timer/Counter2 Output Compare A. The pin has to be ...

  • Page 88

    INT0/RXD1/PCINT26 – Port D, Bit 2 INT0, External Interrupt source 0. The PD2 pin can serve as an external interrupt source to the MCU. RXD1, RXD0, Receive Data (Data input pin for the USART1). When the USART1 receiver is ...

  • Page 89

    Table 12-14. Overriding Signals for Alternate Functions in PD3:PD0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: 8059D–AVR–11/09 PD3/INT1/TXD1/ PD2/INT0/RXD1/ PCINT27 PCINT26 0 0 PORTD2 • PUD 0 RXEN1 ...

  • Page 90

    Register Description 12.3.5 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn ...

  • Page 91

    PORTC – Port C Data Register Bit 0x08 (0x28) Read/Write Initial Value 12.3.13 DDRC – Port C Data Direction Register Bit 0x07 (0x27) Read/Write Initial Value 12.3.14 PINC – Port C Input Pins Address Bit 0x06 (0x26) Read/Write Initial ...

  • Page 92

    Timer/Counter0 with PWM 13.1 Features • Two Independent Output Compare Units • Double Buffered Output Compare Registers • Clear Timer on Compare Match (Auto Reload) • Glitch Free, Phase Correct Pulse Width Modulator (PWM) • Variable PWM Period ...

  • Page 93

    The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk The double buffered Output Compare Registers (OCR0A and ...

  • Page 94

    Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = ...

  • Page 95

    Figure 13-3. Output Compare Unit, Block Diagram The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou- ble buffering is ...

  • Page 96

    Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of ...

  • Page 97

    Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x1 tells the Waveform Generator that no action on the OC0x Register ...

  • Page 98

    Figure 13-5. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be ...

  • Page 99

    PWM mode is shown in togram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Com- pare Matches between OCR0x and TCNT0. Figure 13-6. Fast PWM ...

  • Page 100

    OC0A toggle in CTC mode, except the double buffer feature of the Out- put Compare unit is enabled in the fast PWM mode. 13.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM02:0 = ...

  • Page 101

    OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See be visible on the port pin if the data direction for the port pin ...

  • Page 102

    Figure 13-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 13-10 mode and PWM mode, where OCR0A is TOP. Figure 13-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f clk clk (clk TCNTn OCRnx OCFnx ...

  • Page 103

    Register Description 13.9.1 TCCR0A – Timer/Counter Control Register A Bit 0x24 (0x44) Read/Write Initial Value • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of ...

  • Page 104

    Table 13-4. COM0A1 Note: • Bits 5:4 – COM0B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits are set, the OC0B output ...

  • Page 105

    Table 13-7 on page 105 to phase correct PWM mode. Table 13-7. COM0B1 Note: • Bits 3:2 – Res: Reserved Bits These bits are reserved bits in the ATmega1284P and will always read as zero. • ...

  • Page 106

    TCCR0B – Timer/Counter Control Register B Bit 0x25 (0x45) Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility ...

  • Page 107

    Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 13-9. CS02 external pin modes are used for ...

  • Page 108

    OCR0B – Output Compare Register B Bit 0x28 (0x48) Read/Write Initial Value The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output ...

  • Page 109

    Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware ...

  • Page 110

    Timer/Counter1 and Timer/Counter3 with PWM 14.1 Features • True 16-bit Design (i.e., Allows 16-bit PWM) • Two independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceler • ...

  • Page 111

    Figure 14-1. 16-bit Timer/Counter Block Diagram Note: 14.2.1 Registers The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Reg- ister (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are ...

  • Page 112

    See Section “14.7” on page Flag (OCFnA/B/C) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the Input Capture ...

  • Page 113

    Assembly Code Examples C Code Examples Note: The assembly code example returns the TCNTn value in the r17:r16 register pair important to notice that accessing 16-bit registers are atomic operations interrupt occurs between the two instructions ...

  • Page 114

    The following code examples show how atomic read of the TCNTn Register contents. Reading any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_ReadTCNTn: C Code Example unsigned ...

  • Page 115

    The following code examples show how atomic write of the TCNTn Register contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNTn: C Code Example void ...

  • Page 116

    Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 14-2 Figure 14-2. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear clk TOP BOTTOM The 16-bit counter is mapped ...

  • Page 117

    The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. 14.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can ...

  • Page 118

    TOP value can be written to the ICRn Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location before the low byte is written ...

  • Page 119

    I/O bit location). For measuring frequency only, the clearing of the ICFn Flag is not required (if an interrupt handler is used). 14.7 Output Compare Units The 16-bit comparator continuously compares ...

  • Page 120

    PWM pulses, thereby making the out- put glitch-free. The OCRnx Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCRnx Buffer ...

  • Page 121

    Compare Match Output Unit The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match. Secondly the COMnx1:0 bits control the OCnx ...

  • Page 122

    Compare Output Mode and Waveform Generation The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COMnx1 tells the Waveform Generator that no action on the OCnx Register ...

  • Page 123

    The timing diagram for the CTC mode is shown in increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared. Figure 14-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can ...

  • Page 124

    PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capaci- tors), ...

  • Page 125

    ICRn value written is lower than the current value of TCNTn. The result will then be that the counter will ...

  • Page 126

    However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by ...

  • Page 127

    OCRnx Registers are written. As the third period shown in TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update ...

  • Page 128

    OCRnA set to MAX). The PWM resolution in bits can be calculated using the following equation: In phase and frequency correct PWM mode the counter is incremented until the counter value matches either ...

  • Page 129

    Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively ...

  • Page 130

    Figure 14-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f Figure 14-12 frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by ...

  • Page 131

    Figure 14-13. Timer/Counter Timing Diagram, with Prescaler (f and ICF n 14.11 Register Description 14.11.1 TCCRnA – Timer/Counter n Control Register A Bit Read/Write Initial Value • Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A • Bit 5:4 ...

  • Page 132

    Table 14-3 on page 132 the fast PWM mode. Table 14-3. COMnA1/COMnB1 Note: Table 14-4 on page 132 the phase correct or the phase and frequency correct, PWM mode. Table 14-4. COMnA1/COMnB1 Note: • Bit 1:0 – WGMn1:0: Waveform Generation ...

  • Page 133

    Table 14-5. Waveform Generation Mode Bit Description WGMn2 WGMn1 Mode WGMn3 (CTCn) (PWMn1 ...

  • Page 134

    When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the Input Cap- ture function is disabled. • Bit 5 – Reserved ...

  • Page 135

    A FOCnA/FOCnB strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB bits are always read as zero. 14.11.4 TCNTnH and TCNTnL –Timer/Counter n ...

  • Page 136

    ICRnH and ICRnL – Input Capture Register n Bit Read/Write Initial Value The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the ICPn pin (or optionally on the Analog Comparator output for ...

  • Page 137

    TIMSK3 – Timer/Counter3 Interrupt Mask Register Bit (0x71) Read/Write Initial Value • Bit 7:6 – Res: Reserved Bits These bits are unused bits in the ATmega1284P, and will always read as zero. • Bit 5 – ICIE3: Timer/Counter3, Input ...

  • Page 138

    ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location. • Bit 4:3 – Res: Reserved Bits These bits are unused bits in the ...

  • Page 139

    Bit 2 – OCF3B: Timer/Counter3, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output Compare Register B (OCR3B). Note that a Forced Output Compare (FOC3B) strobe ...

  • Page 140

    Timer/Counter2 with PWM and Asynchronous Operation 15.1 Features • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Frequency Generator • 10-bit Clock Prescaler • Overflow and ...

  • Page 141

    Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit reg- isters. Interrupt request (abbreviated to Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer ...

  • Page 142

    Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 15-2 shows a block diagram of the counter and its surrounding environment. Figure 15-2. Counter Unit Block Diagram Signal description (internal signals): count direction ...

  • Page 143

    WGM22:0 bits and Compare Output mode (COM2x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation ...

  • Page 144

    Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the Output Compare channel, independently of whether ...

  • Page 145

    Register bit for the OC2x pin (DDR_OC2x) must be set as output before the OC2x value is visi- ble on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin ...

  • Page 146

    The timing diagram for the CTC mode is shown in (TCNT2) increases until a compare match occurs between TCNT2 and OCR2A, and then coun- ter (TCNT2) is cleared. Figure 15-5. CTC Mode, Timing Diagram TCNTn OCnx (Toggle) Period An interrupt ...

  • Page 147

    DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The ...

  • Page 148

    A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The waveform generated will have a maximum frequency of ...

  • Page 149

    In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM2x1:0 to ...

  • Page 150

    Figure 15-8. Timer/Counter Timing Diagram, no Prescaling clk clk (clk TCNTn TOVn Figure 15-9 on page 150 Figure 15-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 15-10 on page 150 Figure 15-10. Timer/Counter Timing Diagram, ...

  • Page 151

    Figure 15-11 on page 151 Figure 15-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- (clk TCNTn (CTC) OCRnx OCFnx 15.9 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When ...

  • Page 152

    OCR2xUB bit returns to zero, the device will never receive a compare match interrupt, and the MCU will not wake up. • If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise Reduction ...

  • Page 153

    Timer/Counter Prescaler Figure 15-12. Prescaler for Timer/Counter2 The clock source for Timer/Counter2 is named clk system I/O clock clk clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, ...

  • Page 154

    When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the WGM22:0 bit setting. are set to a normal or CTC mode (non-PWM). Table 15-2. COM2A1 Table 15-3 mode. Table 15-3. ...

  • Page 155

    When OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the WGM22:0 bit setting. are set to a normal or CTC mode (non-PWM). Table 15-5. COM2B1 Table 15-6 mode. Table 15-6. ...

  • Page 156

    Bits 1:0 – WGM21:0: Waveform Generation Mode Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of wave- form ...

  • Page 157

    Bit 6 – FOC2B: Force Output Compare B The FOC2B bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is ...

  • Page 158

    Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match between TCNT2 and the OCR2x Registers. 15.11.4 OCR2A – Output Compare Register A Bit (0xB3) Read/Write Initial ...

  • Page 159

    Bit 2 – OCR2BUB: Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set. When OCR2B has been updated from the temporary storage register, this bit is cleared by hard- ware. A ...

  • Page 160

    TIFR2 – Timer/Counter2 Interrupt Flag Register Bit 0x17 (0x37) Read/Write Initial Value • Bit 2 – OCF2B: Output Compare Flag 2 B The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the data ...

  • Page 161

    SPI – Serial Peripheral Interface 16.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write ...

  • Page 162

    The interconnection between Master and Slave CPUs with SPI is shown in tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the ...

  • Page 163

    When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Functions” on page Table 16-1. Pin MOSI MISO SCK SS Note: The following code examples show how to initialize the ...

  • Page 164

    Assembly Code Example SPI_MasterInit: SPI_MasterTransmit: Wait_Transmit: C Code Example void SPI_MasterInit(void void SPI_MasterTransmit(char cData Note: 8059D–AVR–11/09 (1) ; Set MOSI and SCK output, all others input r17,(1<<DD_MOSI)|(1<<DD_SCK) ldi out DDR_SPI,r17 ; Enable SPI, Master, set clock ...

  • Page 165

    The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 8059D–AVR–11/09 (1) ; ...

  • Page 166

    SS Pin Functionality 16.3.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so ...

  • Page 167

    Table 16-2. SPI Mode Figure 16-3. SPI Transfer Format with CPHA = 0 Figure 16-4. SPI Transfer Format with CPHA = 1 8059D–AVR–11/09 SPI Modes Conditions 0 CPOL=0, CPHA=0 1 CPOL=0, CPHA=1 2 CPOL=1, CPHA=0 3 CPOL=1, CPHA=1 SCK (CPOL ...

  • Page 168

    Register Description 16.5.1 SPCR – SPI Control Register Bit 0x2C (0x4C) Read/Write Initial Value • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is ...

  • Page 169

    Bits 1:0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK ...

  • Page 170

    SPDR – SPI Data Register Bit 0x2E (0x4E) Read/Write Initial Value The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. ...

  • Page 171

    USART 17.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with ...

  • Page 172

    Figure 17-1. USART Block Diagram Note: The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units. The Clock Generation ...

  • Page 173

    UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCKn pin is only active when using synchronous ...

  • Page 174

    Table 17-1. Operating Mode Asynchronous Normal mode (U2Xn = 0) Asynchronous Double Speed mode (U2Xn = 1) Synchronous Master mode f OSC UBRRn Some examples of UBRRn values for some system clock frequencies are found in page 194. 17.4.2 Double ...

  • Page 175

    CPU clock period delay and therefore the maximum external XCKn clock frequency is limited by the following equation: Note that f add some margin to avoid possible loss of data due to frequency variations. 17.4.4 Synchronous Clock ...

  • Page 176

    Figure 17-4. Frame Formats St ( IDLE The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing ...

  • Page 177

    Note that the TXCn Flag must be cleared before each transmission (before UDRn is written used for this purpose. The following simple USART initialization code examples ...

  • Page 178

    Sending Frames with Data Bit A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the transmit buffer by writing to the UDRn I/O location. The ...

  • Page 179

    Assembly Code Example USART_Transmit: C Code Example void USART_Transmit( unsigned int data ) { } Notes: The ninth bit can be used for indicating an address frame when using multi processor communi- cation mode or for other protocol handling as ...

  • Page 180

    Data Register Empty interrupt routine must either write new data to UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The ...

  • Page 181

    Assembly Code Example USART_Receive: C Code Example unsigned char USART_Receive( void ) { } Note: The function simply waits for data to be present in the receive buffer by checking the RXCn Flag, before reading the buffer and returning the ...

  • Page 182

    Assembly Code Example USART_Receive: USART_ReceiveNoError: C Code Example unsigned int USART_Receive( void ) { } Note: The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive ...

  • Page 183

    Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buf- fer. This flag is one when unread ...

  • Page 184

    The Parity Error (UPEn) Flag can then be read by software to check if the frame had a Parity Error. The UPEn bit is set if the next character that can be read ...

  • Page 185

    Double Speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done when the RxDn line is idle (i.e., no communication activity). Figure 17-5. Start Bit Sampling Sample (U2X = 0) Sample ...

  • Page 186

    Figure 17-7. Stop Bit Sampling and Next Start Bit Sampling The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 ...

  • Page 187

    Table 17-2. # (Data+Parity Bit) Table 17-3. # (Data+Parity Bit) The recommendations of the maximum receiver baud rate error was made under the assump- tion that the Receiver and Transmitter equally divides the maximum total error. There are two possible ...

  • Page 188

    When the frame type bit is zero the frame is a data frame. The Multi-processor Communication mode enables several slave MCUs to ...

  • Page 189

    Register Description 17.11.1 UDRn – USART I/O Data Register n Bit Read/Write Initial Value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn. ...

  • Page 190

    Data Register Empty interrupt (see description of the UDRIEn bit).UDREn is set after a reset to indicate that the Transmitter is ready. • Bit 4 – FEn: Frame Error This bit is set if the next character in the receive ...

  • Page 191

    Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable n Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only if the UDRIEn bit is written to one, ...

  • Page 192

    Bits 5:4 – UPMn1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will ...

  • Page 193

    Bit 0 – UCPOLn: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets the relationship between data output change and data input sample, and ...

  • Page 194

    Examples of Baud Rate Setting For standard crystal and resonator frequencies, the most commonly used baud rates for asyn- chronous operation can be generated by using the UBRR settings in UBRR values which yield an actual baud rate differing ...

  • Page 195

    Table 17-10. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% ...

  • Page 196

    Table 17-11. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% ...

  • Page 197

    Table 17-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 16.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% ...

  • Page 198

    USART in SPI Mode 18.1 Features • Full Duplex, Three-wire Synchronous Data Transfer • Master Operation • Supports all four SPI Modes of Operation (Mode and 3) • LSB First or MSB First Data Transfer (Configurable ...

  • Page 199

    BAUD f OSC UBRRn 18.4 SPI Data Modes and Timing There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are ...

  • Page 200

    The UDORDn bit in UCSRnC sets the frame format used by the USART in MSPIM mode. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for ...