ATmega162 Atmel Corporation, ATmega162 Datasheet - Page 28

• Manufacturer Part Number: ATmega162
• Manufacturer: Atmel Corporation

Specifications of ATmega162

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 35
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 6
• Input Capture Channels: 2
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Pull-up and Bus
Keeper
Timing
28
ATmega162/V
The pull-up resistors on the AD7:0 ports may be activated if the corresponding Port register is
written to one. To reduce power consumption in sleep mode, it is recommended to disable the
pull-ups by writing the Port register to zero before entering sleep.
The XMEM interface also provides a bus keeper on the AD7:0 lines. The Bus Keeper can be dis-
abled and enabled in software as described in
32. When enabled, the Bus Keeper will keep the previous value on the AD7:0 bus while these
lines are tri-stated by the XMEM interface.
External memory devices have various timing requirements. To meet these requirements, the
ATmega162 XMEM interface provides four different wait-states as shown in
tant to consider the timing specification of the external memory device before selecting the wait-
state. The most important parameters are the access time for the external memory in conjunc-
tion with the set-up requirement of the ATmega162. The access time for the external memory is
defined to be the time from receiving the chip select/address until the data of this address actu-
ally is driven on the bus. The access time cannot exceed the time from the ALE pulse is asserted
low until data must be stable during a read sequence (t
121 on page
possible to divide the external memory space in two sectors with individual wait-state settings.
This makes it possible to connect two different memory devices with different timing require-
ments to the same XMEM interface. For XMEM interface timing details, please refer to
118
Note that the XMEM interface is asynchronous and that the waveforms in the figures below are
related to the internal system clock. The skew between the internal and external clock (XTAL1)
is not guaranteed (it varies between devices, temperature, and supply voltage). Consequently,
the XMEM interface is not suited for synchronous operation.
Figure 13. External Data Memory Cycles without Wait-state
Note:
to
Figure
System Clock (CLK
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or
(SRWn1 = 0 and SRWn0 =0)
SRW00 (lower sector).
The ALE pulse in period T4 is only present if the next instruction accesses the RAM (internal
or external).
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
272). The different wait-states are set up in software. As an additional feature, it is
121, and
DA7:0
A15:8
CPU
ALE
WR
RD
Table 114
)
Prev. addr.
Prev. data
Prev. data
to
T1
Table
(1)
121.
Address
Address
Address
“Special Function IO Register – SFIOR” on page
T2
XX
LLRL
+ t
Address
T3
Data
Data
Data
RLRH
- t
DVRH
T4
in
Table
Table 114
2513K–AVR–07/09
3. It is impor-
to
Figure
Table