ATmega162 Atmel Corporation, ATmega162 Datasheet - Page 85

• Manufacturer Part Number: ATmega162
• Manufacturer: Atmel Corporation

Specifications of ATmega162

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 35
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 6
• Input Capture Channels: 2
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Extended MCU
Control Register –
EMCUCR
2513K–AVR–07/09
Table 43. Interrupt 1 Sense Control
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate
an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
selected, the low level must be held until the completion of the currently executing instruction to
generate an interrupt.
Table 44. Interrupt 0 Sense Control
• Bit 0 – ISC2: Interrupt Sense Control 2
The asynchronous External Interrupt 2 is activated by the external pin INT2 if the SREG I-bit and
the corresponding interrupt mask in GICR are set. If ISC2 is cleared (zero), a falling edge on
INT2 activates the interrupt. If ISC2 is set (one), a rising edge on INT2 activates the interrupt.
Edges on INT2 are registered asynchronously. Pulses on INT2 wider than the minimum pulse
width given in
an interrupt. When changing the ISC2 bit, an interrupt can occur. Therefore, it is recommended
to first disable INT2 by clearing its Interrupt Enable bit in the GICR Register. Then, the ISC2 bit
can be changed. Finally, the INT2 Interrupt Flag should be cleared by writing a logical one to its
Interrupt Flag bit (INTF2) in the GIFR Register before the interrupt is re-enabled.
Table 45. Asynchronous External Interrupt Characteristics
Bit
Read/Write
Initial Value
Symbol
ISC11
ISC01
t
INT
0
0
1
1
0
0
1
1
Parameter
Minimum pulse width for
asynchronous external interrupt
ISC10
ISC00
Table 45
0
1
0
1
0
1
0
1
SM0
R/W
7
0
Description
The low level of INT1 generates an interrupt request.
Any logical change on INT1 generates an interrupt request.
The falling edge of INT1 generates an interrupt request.
The rising edge of INT1 generates an interrupt request.
Description
The low level of INT0 generates an interrupt request.
Any logical change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
SRL2
R/W
Table
will generate an interrupt. Shorter pulses are not guaranteed to generate
6
0
44. The value on the INT0 pin is sampled before detecting edges.
SRL1
R/W
5
0
SRL0
R/W
4
0
SRW01
R/W
Condition
3
0
SRW00
R/W
2
0
Min.
SRW11
R/W
1
0
Typ.
50
ATmega162/V
ISC2
R/W
0
0
Max.
EMCUCR
Units
ns
85