ATmega164P Automotive Atmel Corporation, ATmega164P Automotive Datasheet - Page 7

• Manufacturer Part Number: ATmega164P Automotive
• Manufacturer: Atmel Corporation

Specifications of ATmega164P Automotive

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5. CPU Core
5.1
5.2
7701E–AVR–02/11
Overview
Architectural Overview
This section discusses the Atmel
CPU core is to ensure correct program execution. The CPU must, therefore, be able to access
memories, perform calculations, control peripherals, and handle interrupts.
Figure 5-1.
In order to maximize performance and parallelism, the AVR
separate memories and buses for program and data. Instructions in the program memory are
executed with a single-level pipelining. While one instruction is being executed, the next
instruction is pre-fetched from the program memory. This concept enables instructions to be
executed in every clock cycle. The program memory is in-system reprogrammable flash
memory.
Control Lines
Instruction
Instruction
Program
Memory
Decoder
Register
Flash
Block Diagram of the AVR Architecture
Atmel ATtiny24/44/84 [Preliminary]
Program
Counter
®
AVR
®
core architecture in general. The main function of the
and Control
EEPROM
Registrers
I/O Lines
Purpose
General
SRAM
Data Bus 8-bit
Status
32 x 8
Data
ALU
®
uses a Harvard architecture, with
Timer/Counter 0
Timer/Counter 1
Serial Interface
Comparator
Watchdog
Universal
Interrupt
Timer
Analog
Unit
7