ATmega3290A Atmel Corporation, ATmega3290A Datasheet - Page 21

• Manufacturer Part Number: ATmega3290A
• Manufacturer: Atmel Corporation

Specifications of ATmega3290A

• Flash (kbytes): 32 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8.2
8.2.1
8284D–AVR–6/11
SRAM Data Memory
Data Memory Access Times
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P
Figure 8-2
The ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P is a complex
microcontroller with more peripheral units than can be supported within the 64 locations
reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 -
0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
T h e
(ATmega329A/329PA/3290A/3290PA/649A/649P/6490A/6490P) data memory locations
address both the Register File, the I/O memory, Extended I/O memory, and the internal data
SRAM. The first 32 locations address the Register File, the next 64 location the standard I/O
memory, then 160 locations of Extended I/O memory, and the next 1024/2048/4096 locations
address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register
File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given
by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and
t h e
ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P are all accessible
through all these addressing modes. The Register File is described in
ter File” on page
Figure 8-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
1 , 0 2 4 / 2 , 0 4 8
shows how the SRAM Memory is organized.
l o w e r
Data Memory Map
15.
1 2 8 0
X 8
160 Ext I/O Reg.
64 I/O Registers
Data Memory
Internal SRAM
b y t e s
32 Registers
(1024 X 8)
(2048 x 8)
(4096 x 8)
( A T m e g a 1 6 9 A / 1 6 9 P A )
o f
0x04FF/0x08FF/0x10FF
0x0000 - 0x001F
0x0020 - 0x005F
0x0060 - 0x00FF
0x0100
i n t e r n a l
CPU
cycles as described in
d a t a
”General Purpose Regis-
a n d
S R A M
Figure
2 3 0 4 / 4 3 5 2
8-3.
i n
t h e
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