ATmega32A Atmel Corporation, ATmega32A Datasheet - Page 12

• Manufacturer Part Number: ATmega32A
• Manufacturer: Atmel Corporation

Specifications of ATmega32A

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

6.5.1
6.6
8155C–AVR–02/11
Instruction Execution Timing
SPH and SPL – Stack Pointer High and Low Register
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 6-4
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 6-4.
Figure 6-5
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Bit
Read/Write
Initial Value
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
shows the internal timing concept for the Register File. In a single clock cycle an ALU
shows the parallel instruction fetches and instruction executions enabled by the Har-
The Parallel Instruction Fetches and Instruction Executions
SP15
R/W
R/W
SP7
15
7
0
0
clk
SP14
CPU
R/W
R/W
SP6
14
6
0
0
SP13
R/W
R/W
SP5
CPU
13
5
0
0
, directly generated from the selected clock source for the
T1
SP12
R/W
R/W
SP4
12
4
0
0
SP11
R/W
R/W
SP3
11
3
0
0
T2
SP10
R/W
R/W
SP2
10
2
0
0
T3
R/W
R/W
SP9
SP1
ATmega32A
9
1
0
0
R/W
R/W
SP8
SP0
8
0
0
0
T4
SPH
SPL
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