ATmega32A Atmel Corporation, ATmega32A Datasheet - Page 124

• Manufacturer Part Number: ATmega32A
• Manufacturer: Atmel Corporation

Specifications of ATmega32A

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

17.7
17.7.1
17.7.2
8155C–AVR–02/11
Modes of Operation
Normal Mode
Clear Timer on Compare Match (CTC) Mode
A change of the COM21:0 bits state will have effect at the first compare match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOC2 strobe bits.
The mode of operation, that is, the behavior of the Timer/Counter and the output compare pins,
is defined by the combination of the Waveform Generation mode (WGM2[1:0]) and Compare
Output mode (COM2[1:0]) bits. The Compare Output mode bits do not affect the counting
sequence, while the Waveform Generation mode bits do. The COM2[1:0] bits control whether
the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-
PWM modes the COM2[1:0] bits control whether the output should be set, cleared, or toggled at
a compare match
For detailed timing information refer to
The simplest mode of operation is the Normal mode (WGM2[1:0] = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-
tom (0x00). In normal operation the Timer/Counter Overflow Flag (
timer clock cycle as the TCNT2 becomes zero. The
bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the
are no special cases to consider in the normal mode, a new counter value can be written
anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the out-
put compare to generate waveforms in normal mode is not recommended, since this will occupy
too much of the CPU time.
In Clear Timer on Compare or CTC mode (WGM2[1:0] = 2), the OCR2 Register is used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter
value (TCNT2) matches the OCR2. The OCR2 defines the top value for the counter, hence also
its resolution. This mode allows greater control of the compare match output frequency. It also
simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in
increases until a compare match occurs between TCNT2 and OCR2, and then counter (TCNT2)
is cleared.
(See “Compare Match Output Unit” on page
TOV2
Flag, the timer resolution can be increased by software. There
“Timer/Counter Timing Diagrams” on page
TOV2
Figure
Flag in this case behaves like a ninth
17-5. The counter value (TCNT2)
123.).
TOV2
) will be set in the same
ATmega32A
128.
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