ATmega48 Atmel Corporation, ATmega48 Datasheet - Page 300

• Manufacturer Part Number: ATmega48
• Manufacturer: Atmel Corporation

Specifications of ATmega48

• Flash (kbytes): 4 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 23
• Ext Interrupts: 24
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 256
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.8.3
Table 28-17. Serial programming instruction set (hexadecimal values).
2545T–AVR–05/11
Instruction/operation
Programming enable
Chip erase (program memory/EEPROM)
Poll RDY/BSY
Load instructions
Load extended address byte
Load program memory page, high byte
Load program memory page, low byte
Load EEPROM memory page (page access)
Read instructions
Read program memory, high byte
Read program memory, low byte
Read EEPROM memory
Read lock bits
Read signature byte
Read fuse bits
Read fuse high bits
Read extended fuse bits
Read calibration byte
Serial programming instruction set
6. Any memory location can be verified by using the Read instruction which returns the con-
7. At the end of the programming session, RESET can be set high to commence normal
8. Power-off sequence (if needed):
Table 28-16. Typical wait delay before writing the next flash or EEPROM location.
Table 28-17
(1)
Symbol
t
t
t
WD_FLASH
WD_EEPROM
WD_ERASE
28-16 on page
programmed.
tent at the selected address at serial output MISO.
operation.
Set RESET to “1”.
Turn V
CC
and
power off.
Figure 28-8 on page 302
300). In a chip erased device, no 0xFF in the data file(s) need to be
Byte 1
$AC
$AC
$4D
$C1
$A0
$F0
$48
$40
$28
$20
$58
$30
$50
$58
$50
$38
0000 00aa
describes the instruction set.
adr MSB
adr MSB
Byte 2
$53
$80
$00
$00
$00
$00
$00
$00
$00
$00
$08
$08
$00
Instruction format
Extended adr
0000 000aa
0000 000aa
aaaa aaaa
ATmega48/88/168
Minimum wait delay
adr LSB
adr LSB
adr LSB
adr LSB
Byte 3
$00
$00
$00
$00
$00
$00
$00
$00
4.5ms
3.6ms
9.0ms
high data byte out
low data byte out
high data byte in
low data byte in
data byte out
data byte out
data byte out
data byte out
data byte out
data byte out
data byte out
data byte out
data byte in
Byte 4
$00
$00
$00
300