ATtiny43U Atmel Corporation, ATtiny43U Datasheet
ATtiny43U
Specifications of ATtiny43U
Related parts for ATtiny43U
ATtiny43U Summary of contents
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... Active Mode, 1 MHz System Clock (Without Boost Converter) 400 µ – Power-Down Mode (Without Boost Converter) 150 Note: 1. See “Data Retention” on page 6 ® 8-Bit Microcontroller (1) for details. 8-bit Microcontroller with 4K Bytes In-System Programmable Flash and Boost Converter ATtiny43U Preliminary Rev. 8048B–AVR–03/09 ...
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... Pin Configurations Figure 1-1. Pinout of ATtiny43U (T1/CLKO/PCINT11) PB (DI/OC1A/PCINT12) (DO/OC1B/PCINT13) (USCK/SCL/PCINT14) 1.1 Pin Descriptions 1.1 Supply voltage. 1.1.2 GND Ground. 1.1.3 Port A (PA7:PA0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source ...
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PA7 which has the RESET capability. To use pin PA7 as an I/O pin, instead of RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port A pins that are externally pulled low will source current if the pull-up ...
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... Overview The ATtiny43U is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny43U achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con- sumption versus processing speed. Figure 2-1. ...
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... On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface conventional non-volatile memory programmer On-chip boot code running on the AVR core. The ATtiny43U AVR is supported by a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. ...
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... PPM over 20 years at 85°C or 100 years at 25°C. 3.4 Disclaimer Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max val- ues will be available after the device is characterized. ATtiny43U 6 8048B–AVR–03/09 ...
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AVR CPU Core 4.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control ...
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... Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. ATtiny43U 8 8048B–AVR–03/09 ...
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SREG - AVR Status Register Bit 0x3F (0x5F) Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter- rupt enable control ...
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... The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in ATtiny43U 10 shows the structure of the 32 general purpose working registers in the ...
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Figure 4-3. X-register Y-register Z-register In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.6 Stack Pointer The Stack is mainly used for storing ...
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... Instruction Fetch 2nd Instruction Execute 3rd Instruction Execute Figure 4-5 on page 12 cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 4-5. Register Operands Fetch ALU Operation Execute ATtiny43U SP15 SP14 SP13 SP7 ...
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Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be ...
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... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATtiny43U 14 ; store SREG value ; disable interrupts during timed sequence ...
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... Since all AVR instructions are bits wide, the Flash is organized as 2048 x 16. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny43U Pro- gram Counter (PC bits wide, thus addressing the 2048 Program memory locations. “Memory Programming” on page 139 Constant tables can be allocated within the entire Program memory address space (see the LPM – ...
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... EEPROM Data Memory The ATtiny43U contains 64 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described ...
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EEPROM Control Register. For a detailed description of Serial data downloading to the EEPROM, see 5.4.1 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in ...
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... Set Programming mode */ EECR = (0<<EEPM1)|(0<<EEPM0) /* Set up address and data registers */ EEAR = ucAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE); /* Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); } ATtiny43U 18 r16, (0<<EEPM1)|(0<<EEPM0) EECR, r16 ; “OSCCAL – Oscillator Calibration Register” on 8048B–AVR–03/09 ...
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The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example unsigned ...
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... General Purpose I/O Registers ATtiny43U contains three General Purpose I/O Registers. These registers can be used for stor- ing any information, and they are particularly useful for storing global variables and status flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions ...
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EEDR – EEPROM Data Register Bit 0x1D (0x3D) Read/Write Initial Value • Bits 7:0 – EEDR[7:0]: EEPROM Data For the EEPROM write operation the EEDR Register contains the data to be written to the EEPROM in the address given ...
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... EEAR Register. 5.6.4 GPIOR2 – General Purpose I/O Register 2 Bit 0x15 (0x35) Read/Write Initial Value 5.6.5 GPIOR1 – General Purpose I/O Register 1 Bit 0x14 (0x34) Read/Write Initial Value 5.6.6 GPIOR0 – General Purpose I/O Register 0 Bit 0x13 (0x33) Read/Write Initial Value ATtiny43U MSB R/W R/W R/W R ...
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System Clock and Clock Options 6.1 Clock Systems and their Distribution Figure 6-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using ...
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... Note: 6.2.1 External Clock To drive the device from an external clock source, CLKI should be driven as shown in on page “0000” (see Table 6-2. Figure 6-2. ATtiny43U 24 Device Clocking Options Select page 24) page page 26) 1. For all fuses “1” means unprogrammed while “0” means programmed. ...
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When this clock source is selected, start-up times are determined by SUT Fuses as shown in Table 6-3. Table 6-3. SUT1.. When applying an external clock required to avoid sudden changes in the applied ...
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... MHz system clock. The default setting ensures every user can make the desired clock source setting using any available programming interface. ATtiny43U 26 below. Start-up times for Internal Calibrated RC Oscillator Clock Selection ...
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... System Clock Prescaler The ATtiny43U has a system clock prescaler, which means the system clock can be divided as described in section to lower system clock frequency and decrease the power consumption at times when require- ments for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...
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... Read/Write Initial Value • Bit 7 – CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is ATtiny43U ...
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CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit. • Bits 3:0 – CLKPS[3:0]: Clock ...
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... Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. ATtiny43U 30 8048B–AVR–03/09 ...
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... This sleep mode basically halts clk allowing the other clocks to run. 8048B–AVR–03/09 for more details. presents the different clock systems in ATtiny43U, and their distribution. Active Clock Domains and Wake-up Sources in the Different Sleep Modes Active Clock Domains X 1 ...
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... The current state of the peripheral is frozenand the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the ATtiny43U 32 32). The sleep mode power consumption will then be at the same level as when level has dropped during the sleep period ...
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Waking up a module, which is done by clearing the bit in PRR, puts the module in the same state as before shutdown. Module shutdown can be used in ...
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... SLEEP instruction and to clear it immediately after waking up. • Bits 4, 3 – SM[1:0]: Sleep Mode Select Bits 2:0 These bits select between the three available sleep modes as shown in Table 7-2. SM1 ATtiny43U 34 ) and the ADC clock (clk I/O “Digital Input Enable and Sleep Modes” on page 66 /2, the input buffer will use excessive power ...
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Table 7-2. • Bit 2 – BODSE: BOD Sleep Enable BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is controlled by a timed sequence. 7.5.2 PRR – Power Reduction Register Bit 0x00 (0x20) ...
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... In order to work properly microcontrollers typically require a supply voltage level that can not be provided by battery packs of less than two or three battery cells. This constraint adds to size, cost and complexity of the design. The integrated boost converter of ATtiny43U bridges the gap between minimum supply voltage of the device and typical output voltages of single-cell stan- dard, alkaline, Lithium, NiCd or NiMH batteries ...
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Figure 8- When the boost converter is not connected the microcontroller can be powered directly from an external source and is then subject to the standard supply voltage limits defined in Characteristics” on page It is recommended to ...
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... V converter enters Start Mode and output voltage, V the converter exits Start Mode and goes into Active Mode. When output voltage exceeds the power-on threshold V troller is released from reset. ATtiny43U 38 Figure 8-3 on page below the shutdown voltage, V BAT , has no effect in this mode. The converter monitors the ...
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Figure 8-4. CONVERTER: MCU CORE: When input voltage V V begins to fall. When converter output voltage, i.e. the supply voltage of the microcontroller, CC falls below V Figure 8-5 output voltage rises above the power-on threshold the microcontroller is ...
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... In this mode of operation the output voltage is constantly regulated. This means a stable output voltage with a low amplitude, high frequency ripple superimposed. See 7 on page The firmware can instruct the converter to leave this mode and enter Stop Mode. See Control of Boost Converter” on page ATtiny43U 40 (see MS 41). ...
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Figure 8-6. 8.3.2 Active Low Current Mode The boost converter enters Active Low Current Mode from Active Regulated Mode when output voltage reaches its maximum and duty cycle is at its minimum. In practice, this means that the load current ...
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... Active Mode and enter Stop Mode, as illustrated in 37. This procedure allows the device to read true battery voltage using the on-board ADC, assess if the voltage is sufficient for the selected battery chemistry and then control the boost converter accordingly. ATtiny43U 42 Typical Output Voltage of Boost Converter at Constant Full Duty Cycle. V ...
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To stop the boost converter, follow the below procedure: 1. Write 110x xxxx to the Power Reduction Register, PRR 2. Within 3 clock cycles of the above, write 10xx xxxx to PRR 3. Within 4 clock cycles of the first ...
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... The corner frequency of the filter can be calculated as follows: BAT Component values are application specific and depend on the stability of the supply voltage. The LPF reduces voltage ripple at the V ally entering Stop Mode. ATtiny43U 44 the switching period of the boost converter. See S for limits. The steady-state duty cycle is calculated as V ⎛ ...
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Too high resistor values may lead to Start Mode failures. See ues” on page 45 Capacitor C 8.6.5 Output Capacitors An output capacitor, C transferred to the inductor recommended to use a capacitor with high capacitance and low ...
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... It is possible to bypass and disable the boost converter so that the device can be powered directly from an external supply. To force the boost converter into Stop Mode, connect pin V to ground and provide the device with supply directly to the V ATtiny43U 46 Recommended Components and Values for Various Designs ...
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V directly to the V 8.11 Register Description 8.11.1 ADCSRB – ADC Control and Status Register B Bit 0x03 (0x23) Read/Write Initial Value • Bit 7 – BS: Boost Status The BS bit can be used ...
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... This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif- ferent selections for the delay period are presented in ATtiny43U 48 Figure 9-1 shows the reset logic. ...
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... Reset Sources The ATtiny43U has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length when RESET function is enabled. ...
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... Figure 9-4. 9.5 Brown-out Detection ATtiny43U has an On-chip Brown-out Detection (BOD) circuit for monitoring the V operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V ...
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... Timer” on page 51 Figure 9-6. 9.7 Internal Voltage Reference ATtiny43U features an internal bandgap reference. This reference is used for Brown-out Detec- tion, and it can be used as an input to the Analog Comparator or the ADC. 9.7.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in turned on ...
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... If the reset period expires without another Watchdog Reset, the ATtiny43U resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can be very helpful when using the Watchdog to wake-up from Power-down ...
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Safety Level 2 In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed sequence is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following ...
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... Watchdog Time-out Interrupt is enabled. In this mode the corresponding interrupt is executed instead of a reset if a timeout in the Watchdog Timer occurs. If WDE is set, WDIE is automatically cleared by hardware when a time-out occurs. This is useful for keeping the Watchdog Reset security while using the interrupt. After the WDIE bit is cleared, ATtiny43U ...
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To avoid the Watchdog Reset, WDIE must be set after each interrupt. Table 9-2. WDE • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when ...
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... The different prescaling values and their corresponding Timeout Periods are shown in Table 9-3 on page Table 9-3. WDP3 ATtiny43U 56 56. Watchdog Timer Prescale Select Number of WDT Oscillator WDP2 WDP1 WDP0 ...
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... Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny43U. For a general explanation of the AVR interrupt handling, see 13. 10.1 Interrupt Vectors Table 10-1. Vector No the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations ...
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... SLEEP command. The start-up time is defined by the SUT and CKSEL fuses, as described in Clock and Clock Options” on page 10.2.1 Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in ATtiny43U 58 rjmp TIM0_COMPA rjmp TIM0_COMPB ...
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Figure 10-1. Timing of pin change interrupts PCINT(0) PCINT(0) pin_lat pin_sync pcint_in_(0) pcint_syn pcint_setflag PCIF 10.3 Register Description 10.3.1 MCUCR – MCU Control Register The External Interrupt Control Register A contains control bits for interrupt sense control. Bit 0x35 (0x55) ...
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... GIFR – General Interrupt Flag Register Bit 0x3A (0x5A) Read/Write Initial Value • Bits 7, 3:0 – Res: Reserved Bits These bits are reserved and will always read zero. ATtiny43U 60 Interrupt 0 Sense Control ISC00 Description 0 The low level of INT0 generates an interrupt request asynchronously ...
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Bit 6 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set ...
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... How each alternate function interferes with the port pin is described in Functions” on page nate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. ATtiny43U 62 and Ground as indicated in CC for a complete list of parameters. ...
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Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. tional description of one I/O-port pin, here generically called Pxn. Figure 11-2. General Digital I/O Pxn Note: 11.2.1 Configuring the Pin Each port pin ...
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... This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. page 65 value. The maximum and minimum propagation delays are denoted t respectively. ATtiny43U 64 summarizes the control signals for the pin value. Port Pin Configurations PUD ...
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Figure 11-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS SYNC LATCH Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and ...
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... SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt ATtiny43U 66 (1) r16,(1<<PA4)|(1<<PA1)|(1<<PA0) r17,(1< ...
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External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change. 11.2.6 Unconnected Pins If some pins are unused, it ...
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... Figure 11-5. Alternate Port Functions Pxn PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: PTOExn: Note: ATtiny43U 68 (1) PUOExn PUOVxn 1 0 DDOExn DDOVxn 1 0 PVOExn PVOVxn 1 0 DIEOExn DIEOVxn 1 SLEEP 0 SYNCHRONIZER ...
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Table 11-2 ure 11-5 on page 68 generated internally in the modules having the alternate function. Table 11-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for ...
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... Port A, Bit 3 – ADC3/PCINT3 ADC3: Analog to Digital Converter, Channel 3 PCINT3: Pin Change Interrupt source 3. The PA3 pin can serve as an external interrupt source for pin change interrupt 0. ATtiny43U 70 Port A Pins Alternate Functions Port Pin Alternate Function ADC0: ADC input channel 0 ...
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Port A, Bit 4 – AIN0/PCINT4 AIN0: Analog Comparator Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. PCINT4: ...
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... DIEOV DI AIO 1. 2. Table 11-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATtiny43U 72 to Table 11-6 on page 73 Figure 11-5 on page Overriding Signals for Alternate Functions in PA7..PA6 dW/ PA7/RESET/ PCINT7 (1) RSTDISBL + MONCOM_ENABLE 1 (1) RSTDISBL + MONCOM_ENABLE MONCOM_ENABLE • debugWire Transmit (1) RSTDISBL ...
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Table 11-6. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 11-7. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 8048B–AVR–03/09 Overriding Signals for Alternate Functions in PA3..PA2 PA3/ADC3/PCINT3 0 ...
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... OC0B: Output Compare Match output: The PB2 pin can serve as an external output for the Timer/Counter0 Compare Match A. The PB2 pin has to be configured as an output (DDB2 set (one)) to serve this function. The OC0B pin is also the output pin for the PWM mode timer function. ATtiny43U 74 Port B Pins Alternate Functions Port Pin ...
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PCINT10: Pin Change Interrupt source 10. The PB2 pin can serve as an external interrupt source for pin change interrupt 1. • Port B, Bit 3 – T1/CLKO/PCINT11 T1: Timer/Counter1 Counter source. CLKO: System Clock Output. The system clock can ...
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... AIO Table 11-10. Overriding Signals for Alternate Functions in PB5..PB4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATtiny43U 76 to Table 11-12 on page 77 Figure 11-5 on page 68. Overriding Signals for Alternate Functions in PB7..PB6 PB7/INT0/PCINT15 (PCINT15 • PCIE1) + INT0 (PCINT15 • ...
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Table 11-11. Overriding Signals for Alternate Functions in PB3..PB2 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 11-12. Overriding Signals for Alternate Functions in PB1..PB0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE ...
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... PORTB – Port B Data Register Bit 0x18 (0x38) Read/Write Initial Value 11.4.6 DDRB – Port B Data Direction Register Bit 0x17 (0x37) Read/Write Initial Value 11.4.7 PINB – Port BInput Pins Address Bit 0x16 (0x36) Read/Write Initial Value ATtiny43U BODS PUD SE SM1 R/W R/W R/W R for more details about this feature ...
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Timer/Counter with PWM (Timer/Counter0 and Timer/Counter1) 12.1 Features • Two Independent Output Compare Units • Double Buffered Output Compare Registers • Clear Timer on Compare Match (Auto Reload) • Glitch Free, Phase Correct Pulse Width Modulator (PWM) • ...
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... Timer/Counter Control Register (TCCRnB). For details on clock sources and pres- caler, see 12.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 12-2 on page 81 ATtiny43U 80 “Output Compare Unit” on page 81 Table 12-1 are used extensively throughout the document. Definitions The counter reaches the BOTTOM when it becomes 0x00 ...
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Figure 12-2. Counter Unit Block Diagram Signal description (internal signals): count direction clear clk top bottom Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select ...
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... TCNTn when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNTn equals the OCRnx value, the Compare Match will be missed, resulting in incorrect waveform ATtiny43U 82 DATA BUS OCRnx ...
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Similarly, do not write the TCNTn value equal to BOTTOM when the counter is down-counting. The setup of the OCnx should be performed before setting the Data Direction Register for the port pin to output. The easiest way of ...
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... OCRnA. The OCRnA defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. ATtiny43U 84 “Register Description” on page 90 Table 12-2 on page Table 12-4 on page “ ...
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The timing diagram for the CTC mode is shown in (TCNTn) increases until a Compare Match occurs between TCNTn and OCRnA, and then coun- ter (TCNTn) is cleared. Figure 12-5. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period An interrupt ...
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... The extreme values for the OCRnA Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCRnA is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCRnA equal to MAX will result ATtiny43U 86 Figure 12-6 on page 86 ...
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COMnA1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OCnx to toggle ...
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... The Timer/Counter is a synchronous design and the timer clock (clk clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. The figure shows the count sequence close to the MAX value in all modes other than phase cor- rect PWM mode. ATtiny43U 88 Table 12-4 on page f OCnxPCPWM ...
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Figure 12-8. Timer/Counter Timing Diagram, no Prescaling clk I/O clk Tn (clk /1) I/O TCNTn TOVn Figure 12-9 on page 89 Figure 12-9. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn TOVn Figure 12-10 ...
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... When OCnA is connected to the pin, the function of the COMnA[1:0] bits depends on the WGMn[2:0] bit setting. WGMn[2:0] bits are set to a normal or CTC mode (non-PWM). Table 12-2. COMnA1 ATtiny43U 90 caler (f /8) clk_I/O TOP - 1 TOP ...
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Table 12-3 on page 91 to fast PWM mode. Table 12-3. COMnA1 Note: Table 12-4 on page 91 to phase correct PWM mode. Table 12-4. COMnA1 Note: • Bits 5:4 – COMnB[1:0]: ...
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... Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see ATtiny43U 92 shows the COMnB[1:0] bit functionality when the WGMn[2:0] bits are set Compare Output Mode, Fast PWM Mode ...
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Table 12-8. Mode Note: 12.9.3 TCCR0B – Timer/Counter Control Register B Bit 0x33 (0x53) Read/Write Initial Value 12.9.4 TCCR1B – Timer/Counter Control Register B Bit 0x2E (0x4E) Read/Write Initial Value • Bit ...
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... If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 12.9.5 TCNT0 – Timer/Counter Register Bit 0x32 (0x52) Read/Write Initial Value ATtiny43U 94 “Register Description” on page Clock Select Bit Description CSn1 CSn0 Description 0 0 ...
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TCNT1 – Timer/Counter Register Bit 0x2D (0x4D) Read/Write Initial Value The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNTn Register blocks (removes) the Compare Match on ...
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... OCRnB – Output Compare Registern B. OCFnB is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCFnB is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIEnB (Timer/Counter Compare B Match Interrupt Enable), and OCFnB are set, the Timer/Countern Compare Match Interrupt is executed. ATtiny43U ...
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Bit 1 – OCFnA: Output Compare Flag n A The OCFnA bit is set when a Compare Match occurs between the Timer/Countern and the data in OCRnA – Output Compare Registern A. OCFnA is cleared by hardware when executing ...
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... Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the sys- ATtiny43U 98 ). Alternatively, one of four taps from the prescaler can be used as a ...
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However, due to variation of the system clock frequency and duty cycle caused by Oscillator source ...
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... The most significant bit of the USI Data Register is connected to one of two output pins (depend- ing on the mode configuration, see between the output of the USI Data Register and the output pin, which delays the change of data ATtiny43U 100 Figure 14-1 on page “Pinout of ATtiny43U” on page 2. CPU accessible I/O Registers, including I/O 107 ...
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The serial input is always sampled from the Data Input (DI) pin independent of the configuration. The 4-bit counter can be both read and written via the data bus, ...
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... The overflow interrupt will wake up the processor set to Idle mode. Depending on the protocol used the slave device can now set its output to high impedance. 14.3.2 SPI Master Operation Example The following code demonstrates how to use the USI module as a SPI Master: SPITransfer: <continues> ATtiny43U 102 ( Reference ) MSB 6 ...
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SPITransfer_loop: The code is size optimized using only eight instructions (plus return). The code example assumes that the DO and USCK pins have been enabled as outputs in DDRA. The value stored in register r16 prior to the function ...
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... This means that the master must always check if the SCL line was actually released after it has generated a positive edge. Since the clock also increments the counter, a counter overflow can be used to indicate that the transfer is completed. The clock is generated by the master by toggling the USCK pin via the PORTA register. ATtiny43U 104 ldi r16,(1<<USIWM0)|(1<<USICS1) out ...
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Figure 14-4. Two-wire Mode Operation, Simplified Diagram Bit7 SLAVE Bit7 MASTER The data direction is not given by the physical layer. A protocol, like the one used by the TWI- bus, must be implemented to control the data flow. Figure ...
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... However, the protocol used might have restrictions on the SCL hold time. Therefore, when using this feature the oscillator start-up time (set by CKSEL fuses, see “Clock Sources” on page of the USISIF bit on ATtiny43U 106 Figure 14-6. The SDA line is delayed (in the range of 50 SDA ...
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Alternative USI Usage The flexible design of the USI allows used for other tasks when serial communication is not needed. Below are some examples. 14.4.1 Half-Duplex Asynchronous Data Transfer Using the USI Data Register in three-wire ...
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... USICLK bit clocks both the USI Data Register and the counter. For external clock source (USICS1 = 1), the USICLK bit is no longer used as a strobe, but selects between external clocking and software clocking by the USITC strobe bit. ATtiny43U 108 Relationship between USIWM[1:0] and USI Operation ...
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Table 14-2 source used for the USI Data Register and the 4-bit counter. Table 14-2. USICS1 • Bit 1 – USICLK: Clock Strobe Writing a one to this bit location strobes the USI ...
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... The shift operation can be synchronised to an external clock edge Timer/Counter0 Compare Match, or directly to software via the USICLK bit serial clock occurs at the same cycle the register is written, the register will contain the value written and no shift is performed. ATtiny43U 110 7 ...
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Note that even when no wire mode is selected (USIWM[1: both the external data input (DI/SDA) and the external clock input (USCK/SCL) can still be used by the USI Data Register. The output pin (DO or SDA, depending ...
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... ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX[1:0] in ADMUX select the input pin to replace the negative input to the Analog Comparator, as shown in 15-1. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog Comparator. ATtiny43U 112 112. ACBG (1) 1 ...
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Table 15-1. ACME 15.2 Register Description 15.2.1 ADCSRB – ADC Control and Status Register B Bit 0x03 (0x23) Read/Write Initial Value • Bit 6 – ACME: Analog Comparator Multiplexer Enable When this bit is ...
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... PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ- ten logic one to reduce power consumption in the digital input buffer. ATtiny43U 114 Table 15-2 ...
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... Interrupt on ADC Conversion Complete • Sleep Mode Noise Cancele 16.2 Overview ATtiny43U features a 10-bit, successive approximation Analog-to-Digital Converter (ADC). A block diagram of the ADC is shown in Figure 16-1. Analog to Digital Converter Block Schematic 8048B–AVR–03/09 ADC Input Voltage Range Figure 8-BIT DATA BUS ...
Page 116
... Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (see description of the ADTS ATtiny43U 116 ) and ground (GND). BAT input pin can be selected as single ended input to the ADC ...
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When a positive edge occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started. This provides a method of starting con- versions at fixed intervals. If ...
Page 118
... ADC Data Registers, and ADIF is set. In Sin- gle Conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge. ATtiny43U 118 ADEN Reset ...
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Figure 16-5. ADC Timing Diagram, Single Conversion Cycle Number ADC Clock ADSC ADIF ADCH ADCL When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as shown in Figure 16-6 this mode, the sample-and-hold takes place ...
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... ADMUX until one ADC clock cycle after ADSC is written. If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when updating the ADMUX Register, in order to control which conversion will be affected by the new settings. ATtiny43U 120 One Conversion 11 ...
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If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or ...
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... If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: • Keep analog signal paths as short as possible. • Make sure analog tracks run over the analog ground plane. ATtiny43U 122 /2) should not be present. The user is advised to remove high fre- ADC ...
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Keep analog tracks well away from high-speed switching digital tracks. • Use the ADC noise canceler function to reduce induced noise from the CPU. • If any port pin is used as a digital output, it mustn’t switch while ...
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... Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 16-11. Integral Non-linearity (INL) Output Code ATtiny43U 124 Gain Error Ideal ADC ...
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Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 16-12. Differential Non-linearity (DNL) • Quantization Error: Due to the ...
Page 126
... ADCSR is set). Table 16-3. • Bits 5:3 – Res: Reserved Bits These bits are reserved and will always read zero. ATtiny43U 126 ° C and the accuracy depends on the method of user cal- Temperature vs. Sensor Output Voltage (Typical Case) -40 ° ...
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Bits 2:0 – MUX[2:0]: Analog Channel Selection Bits The value of these bits selects which analog input is connected to the ADC, as shown in 16-4. Selecting channel ADC4 enables temperature measurement. Table 16-4. Notes: If these bits are ...
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... ADC. Table 16-5. ADPS2 16.13.3 ADCL and ADCH – ADC Data Register 16.13.3.1 ADLAR = 0 Bit 0x05 (0x25) 0x04 (0x24) Read/Write Initial Value 16.13.3.2 ADLAR = 1 Bit 0x05 (0x25) 0x04 (0x24) Read/Write Initial Value ATtiny43U 128 ADC Prescaler Selections ADPS1 ...
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When an ADC conversion is complete, the result is found in these two registers. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than ...
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... The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC[3:0] pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. ATtiny43U 130 ADC Auto Trigger Source Selections (Continued) ...
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On-chip Debug System 17.1 Features • Complete Program Flow Control • Emulates All On-chip Functions, Both Digital and Analog , except RESET Pin • Real-time Operation • Symbolic Debugging Support (Both at C and Assembler Source Level, or ...
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... Read/Write Initial Value The DWDR Register provides a communication channel from the running program in the MCU to the debugger. This register is only accessible by the debugWIRE and can therefore not be used as a general purpose register in the normal operations. ATtiny43U 132 will not work. CC ® ...
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Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associ- ated protocol to read code and write (program) that code ...
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... Page Erase and Page Write operation. The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used. Figure 18-1. Addressing the Flash During SPM Z - REGISTER Note: ATtiny43U 134 Z15 ...
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EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation recommended ...
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... Preload SPMCSR bits into R16, then write to SPMCSR ldi out SPMCSR, r16 ; Issue LPM. Table data will be returned into r17 lpm r17, Z ret Note: If successful, the contents of the destination register are as described in section ture Imprint Table” on page ATtiny43U 136 FHB7 FHB6 FHB5 Table 19-4 on page 140 for detailed description and mapping of the Fuse High Byte ...
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Preventing Flash Corruption During periods of low V too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be ...
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... SPMEN bit remains high until the operation is completed. Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower five bits will have no effect. ATtiny43U 138 “EEPROM Write Prevents Writing to SPMCSR” on page 135 for details. 8048B– ...
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... This section describes the different methods for Programming the ATtiny43U memories. 19.1 Program And Data Memory Lock Bits The ATtiny43U provides two Lock bits which can be left unprogrammed (“1”) or can be pro- grammed (“0”) to obtain the additional security listed in can only be erased to “1” with the Chip Erase command. ...
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... Fuse Bytes The ATtiny43U has three Fuse bytes. functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed.. Table 19-3. Fuse High Byte SELFPRGEN Notes: Table 19-4. ...
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Table 19-5. Fuse Low Byte CKDIV8 CKOUT SUT1 SUT0 CKSEL3 CKSEL2 CKSEL1 CKSEL0 Notes: Note that fuse bits are locked if Lock Bit 1 (LB1) is programmed. Fuse bits should be pro- grammed before lock bits. The status of fuse ...
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... ATtiny43U 19.5 Parallel Programming Parameters, Pin Mapping, and Commands This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATtiny43U. Pulses are assumed least 250 ns unless otherwise noted. 19.5.1 Signal Names ...
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Figure 19-1. Parallel Programming Table 19-10. Pin Name Mapping Signal Name in Programming Mode XA1/BS2 PAGEL/BS1 RDY/BSY DATA I/O Table 19-11. Pin Values Used to Enter Programming Mode 8048B–AVR–03/09 WR PA0 XA0 PA1 XA1/BS2 PA2 PAGEL/BS1 PA3 OE PA4 RDY/BSY ...
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... RESET, will cause the device to fail entering programming mode. 5. Wait at least 50 µs before sending a new command. 19.6.2 Considerations for Efficient Programming The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered. ATtiny43U 144 Table 19-12. XA0 Action when CLKI is Pulsed 0 Load Flash or EEPROM Address (High or low address byte determined by BS1) ...
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The command needs only be loaded once when writing or reading multiple memory locations. • Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the EESAVE Fuse is programmed) and Flash after a ...
Page 146
... Set XA1, XA0 to “10”. This enables command loading. 2. Set DATA to “0000 0000”. This is the command for No Operation. 3. Give CLKI a positive pulse. This loads the command, and the internal write signals are reset. ATtiny43U 146 Figure 19-2 on page 147. Note that if less than Figure 19-3 for signal waveforms) ...
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Figure 19-2. Addressing the Flash Which is Organized in Pages Note: Figure 19-3. Programming the Flash Waveforms XA1/BS2 Note: 19.6.5 Programming the EEPROM The EEPROM is organized in pages, see EEPROM, the program data is latched into a page buffer. ...
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... A: Load Command “0000 0011” Load Address High Byte (0x00 - 0xFF Load Address Low Byte (0x00 - 0xFF). 4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA. 5. Set OE to “1”. ATtiny43U 148 ...
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Programming the Fuse Low Bits The algorithm for programming the Fuse Low bits is as follows (refer to on page 145 1. A: Load Command “0100 0000” Load Data Low Byte. Bit n = “0” programs and ...
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... Set OE to “0”, and BS to “0”. The selected Signature byte can now be read at DATA. 4. Set OE to “1”. 19.6.14 Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows (refer to page 145 ATtiny43U 150 for details on Command loading): 0 Fuse Low Byte Extended Fuse Byte ...
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A: Load Command “0000 1000” Load Address Low Byte, 0x00. 3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA. 4. Set OE to “1”. 19.7 Serial Programming Both ...
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... Serial Programming Algorithm When writing serial data to the ATtiny43U, data is clocked on the rising edge of SCK. When reading data from the ATtiny43U, data is clocked on the falling edge of SCK. See 20-6 and To program and verify the ATtiny43U in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in 1 ...
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Power-off sequence (if needed): Set RESET to “1”. Turn V Table 19-15. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol t WD_FLASH t WD_EEPROM t WD_ERASE t WD_FUSE 19.7.2 Serial Programming Instruction set Table 19-16 ...
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... Load EEPROM Memory Page (page access) Byte 1 Byte 2 Byte 3 A Adr dr M Adr MSB Bit 15 B ATtiny43U 154 Byte 1 $AC $AC $AC 1. Not all instructions are applicable for all parts address 3. Bits are programmed ‘0’, unprogrammed ‘1’. ...
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Electrical Characteristics 20.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0. Voltage on RESET with respect to Ground......-0.5V to +13.0V ...
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... If I guaranteed. Pins are not guaranteed to source currents greater than those listed. 7. See “Boost Converter Characteristics” on page 159 20.3 Speed Grades Figure 20-1. Maximum Frequency vs MHz 4 MHz 1.8V ATtiny43U 156 = -40°C to 85°C (Continued) A Condition 5 input low CC 5 ...
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Clock Characteristics 20.4.1 Calibrated Internal Oscillator Accuracy It is possible to manually calibrate the internal oscillator to be more accurate than default factory calibration. Please note that the oscillator frequency depends on temperature and voltage. Table 20-2. Calibration Accuracy ...
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... BOT a voltage where correct operation of the microcontroller is no longer guaranteed. 20.6 External Interrupt Characteristics Table 20-6. Characteristics of Asynchronous External Interrupt Symbol Parameter t Minimum pulse width for asynchronous external interrupt INT ATtiny43U 158 Condition T = -40 - 85° -40 - 85° -40 - 85° ...
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Boost Converter Characteristics Table 20-7. Characteristics of Boost Converter -20°C ... +85°C, unless otherwise noted Symbol Parameter V Start Voltage START V Input Voltage BAT V Shutdown Voltage STOP V BOOST V Output Voltage CC I Load ...
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... Differential Non-linearity (DNL) Gain Error Offset Error Conversion Time Clock Frequency V Input Voltage IN Input Bandwidth V Internal Voltage Reference INT R Analog Input Resistance AIN ATtiny43U 160 = -40°C - 85°C, Boost Converter Disabled. A Condition Min 4V, REF CC ADC clock = 200 kHz 4V, REF ...
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Table 20-9. ADC Characteristics, Single_Ended Conversion, T Symbol Parameter Resolution Absolute accuracy (Including INL, DNL, and quantization, Gain and Offset Errors) Integral Non-linearity (INL) (Accuracy after Offset and Gain Calibration) Differential Non-linearity (DNL) Gain Error Offset Error Conversion Time Clock ...
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... Note: The timing requirements in Figure 20-3 Figure 20-4. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements LOAD ADDRESS (LOW BYTE) t XLOL CLKI PAGEL/BS1 OE DATA ADDR0 (Low Byte) XA0 XA1/BS2 ATtiny43U 162 t XLWL t XHXL t t DVXH XLDX t t BVPH PLBX t PLWL (i ...
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Figure 20-5. Parallel Programming Timing, Loading Sequence with Timing Requirements LOAD ADDRESS (LOW BYTE) CLKI PAGEL/BS1 DATA ADDR0 (Low Byte) XA0 XA1/BS2 Table 20-10. Parallel Programming Characteristics, V Symbol Parameter V Programming Enable Voltage PP I Programming Enable Current PP ...
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... CC t SCK Pulse Width High SHSL t SCK Pulse Width Low SLSH t MOSI Setup to SCK High OVSH t MOSI Hold after SCK High SHOX t SCK Low to MISO Valid SLIV ATtiny43U 164 t t OVSH SHOX t SHSL MSB MSB = -40°C to 85° 4.5V - 5.5V 4.5V - 5.5V) t SLSH ...
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Typical Characteristics – TBD The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indica- tions of how the ...
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... Figure 21-2. Boost Converter Efficiency vs. Load Current and Figure 21-3. Input Voltage Required to Maintain Regulation vs. Load Current ATtiny43U 166 BOOST CONVERTER EFFICIENCY vs. LOAD CURRENT 0 10 Load Current (mA) TYPICAL V VOLTAGES REQUIRED TO MAINTAIN OUTPUT REGULATION BAT 1.2 1.1 1.0 0.9 0.8 0.7 0 Voltage BAT V = 0.7 V BAT 20 20 Load Current (mA ...
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Register Summary Address Name Bit 7 0x3F (0x5F) SREG I – 0x3E (0x5E) SPH 0x3D (0x5D) SPL SP7 0x3C (0x5C) OCR0B 0x3B (0x5B) GIMSK – 0x3A (0x5A) GIFR – 0x39 (0x59) TIMSK0 – 0x38 (0x58) TIFR0 – 0x37 (0x57) ...
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... Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. ATtiny43U 168 8048B–AVR–03/09 ...
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Instruction Set Summary Mnemonics Operands ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract ...
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... Push Register on Stack POP Rd Pop Register from Stack MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break ATtiny43U 170 Description Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Rd(n) ← Rd(n+1), n=0..6 Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) SREG(s) ← 1 SREG(s) ← ← Rr(b) Rd(b) ← ← ← ← ← ...
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... Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 20S2 20-lead, 0.300" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) 8048B–AVR–03/09 (1) Ordering Code ATtiny43U-MU (3) ATtiny43U-SU “Characteristics of Boost Converter -20°C ... +85°C, unless other- for more information. Package Type (2) Package Operational Range 20M1 ...
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... D2 Pin #1 Notch (0. BOTTOM VIEW Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. Note: 2325 Orchard Parkway San Jose, CA 95131 R ATtiny43U 172 TITLE 20M1, 20-pad 0.8 mm Body, Lead Pitch 0.50 mm, 2.6 mm Exposed Pad, Micro Lead Frame Package (MLF) ...
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25.2 20S2 8048B–AVR–03/09 173 ...
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... Errata The revision letter in this section refers to the revision of the ATtiny43U device. 26.1 ATtiny43U 26.1.1 Rev. C • Increased Probability of Boost Converter Entering Active Low Current Mode 1. Increased Probability of Boost Converter Entering Active Low Current Mode The boost converter may enter and stay in Active Low Current Mode at supply voltages and load currents higher than those specified ...
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Datasheet Revision History 27.1 Rev. 8048B-03/09 1. 27.2 Rev. 8048A-02/09 1. 8048B–AVR–03/09 Updated Data retention bullet in “Features” on page Initial revision. 1. 175 ...
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... ATtiny43U 176 8048B–AVR–03/09 ...
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Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 2 Overview ................................................................................................... 4 3 About ......................................................................................................... 6 4 AVR CPU Core .......................................................................................... 7 5 Memories ................................................................................................ 15 6 System Clock and Clock Options ......................................................... 23 7 Power Management ...
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... Power Supply and On-Chip Boost Converter ...................................... 36 9 System Control and Reset .................................................................... 48 10 Interrupts ................................................................................................ 57 11 I/O Ports .................................................................................................. 62 ATtiny43U ii 7.1 Sleep Modes ....................................................................................................31 7.2 Software BOD Disable .....................................................................................32 7.3 Power Reduction Register ...............................................................................32 7.4 Minimizing Power Consumption ......................................................................33 7.5 Register Description ........................................................................................34 8.1 Overview ..........................................................................................................36 8.2 Modes of Operation .........................................................................................37 8.3 Output Voltage versus Load Current ...............................................................40 8.4 Overload Behaviour .........................................................................................42 8.5 Software Control of Boost Converter ...............................................................42 8 ...
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Timer/Counter with PWM (Timer/Counter0 and Timer/Counter1 Timer/Counter Prescaler ....................................................................... 98 14 USI – Universal Serial Interface .......................................................... 100 15 Analog Comparator ............................................................................. 112 16 Analog to Digital Converter ................................................................ 115 8048B–AVR–03/09 11.4 Register Description ........................................................................................78 ...
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... On-chip Debug System .................................................. 131 18 Self-Programming the Flash ............................................................... 133 19 Memory Programming ......................................................................... 139 20 Electrical Characteristics .................................................................... 155 ATtiny43U iv 16.10 ADC Accuracy Definitions .............................................................................123 16.11 ADC Conversion Result .................................................................................125 16.12 Temperature Measurement ...........................................................................125 16.13 Register Description ......................................................................................126 17.1 Features ........................................................................................................131 17.2 Overview ........................................................................................................131 17.3 Physical Interface ..........................................................................................131 17.4 Software Break Points ...................................................................................132 17 ...
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... External Interrupt Characteristics ..................................................................158 20.7 Boost Converter Characteristics ....................................................................159 20.8 ADC Characteristics – Preliminary Data ........................................................160 20.9 Parallel Programming Characteristics ...........................................................162 20.10 Serial Programming Characteristics ..............................................................164 21.1 Boost Converter .............................................................................................165 24.1 ATtiny43U ......................................................................................................171 25.1 20M1 ..............................................................................................................172 25.2 20S2 ..............................................................................................................173 26.1 ATtiny43U ......................................................................................................174 27.1 Rev. 8048B-03/09 ..........................................................................................175 27.2 Rev. 8048A-02/09 ..........................................................................................175 v ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2009 Atmel Corporation. All rights reserved. Atmel Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia Atmel Europe Unit 1-5 & ...