ATtiny43U Atmel Corporation, ATtiny43U Datasheet - Page 99

• Manufacturer Part Number: ATtiny43U
• Manufacturer: Atmel Corporation

Specifications of ATtiny43U

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 8 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 0.7 to 5.5
• Operating Voltage (vcc): 0.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

13.3
13.3.1
8048B–AVR–03/09
Register Description
GTCCR – General Timer/Counter Control Register
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
An external clock source can not be prescaled.
Figure 13-2. Prescaler for Timer/Countern
Note:
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSR10 bit is kept, hence keeping the Prescaler Reset signal asserted.
This ensures that the Timer/Counter is halted and can be configured without the risk of advanc-
ing during configuration. When the TSM bit is written to zero, the PSR10 bit is cleared by
hardware, and the Timer/Counter start counting.
• Bit 0 – PSR10: Prescaler Reset Timer/Counter
When this bit is one, the Timer/Counter prescaler will be reset. This bit is normally cleared imme-
diately by hardware, except if the TSM bit is set.
Bit
0x23 (0x43)
Read/Write
Initial Value
PSR10
clk
Tn
1. The synchronization logic on the input pins (
I/O
Synchronization
TSM
R/W
7
0
ExtClk
R
6
–
0
< f
clk_I/O
Clear
/2) given a 50/50% duty cycle. Since the edge detector uses
R
5
–
0
R
4
–
0
CSn0
CSn1
CSn2
Tn)
is shown in
R
3
–
0
TIMER/COUNTERn CLOCK SOURCE
0
R
2
–
0
Figure 13-1 on page
clk
Tn
R
1
–
0
PSR10
clk_I/O
R/W
0
0
98.
/2.5.
GTCCR
99