ATxmega128A3 Atmel Corporation, ATxmega128A3 Datasheet

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ATxmega128A3

Manufacturer Part Number
ATxmega128A3
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega128A3

Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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This document contains complete and detailed description of all modules included in
the AVR® XMEGA
high performance and peripheral rich CMOS 8/16-bit microcontrollers based on the
AVR enhanced RISC architecture. The available XMEGA A modules described in this
manual are:
AVR CPU
Memories
DMA - Direct Memory Access Controller
Event System
System Clock and Clock options
Power Management and Sleep Modes
System Control and Reset
Battery Backup System
WDT - Watchdog Timer
Interrupts and Programmable Multi-level Interrupt Controller
PORT - I/O Ports
TC - 16-bit Timer/Counter
AWeX - Advanced Waveform Extension
Hi-Res - High Resolution Extension
RTC - Real Time Counter
RTC32 - 32-bit Real Time Counter
TWI - Two Wire Serial Interface
SPI - Serial Peripheral Interface
USART - Universal Synchronous and Asynchronous Serial Receiver and Transmitter
IRCOM - IR Communication Module
AES and DES Crypto Engine
EBI - External Bus Interface
ADC - Analog to Digital Converter
DAC - Digital to Analog Converter
AC - Analog Comparator
IEEE 1149.1 JTAG Interface
PDI - Program and Debug Interface
Memory Programming
Peripheral Address Map
Register Summary
Interrupt Vector Summary
Instruction Set Summary
TM
A Microcontroller family. The XMEGA A is a family of low power,
8-bit
XMEGA A
Microcontroller
XMEGA A
MANUAL
Preliminary
8077H- AVR-12/09

Related parts for ATxmega128A3

ATxmega128A3 Summary of contents

Page 1

This document contains complete and detailed description of all modules included in TM the AVR® XMEGA A Microcontroller family. The XMEGA family of low power, high performance and peripheral rich CMOS 8/16-bit microcontrollers based on the AVR ...

Page 2

About the Manual This document contains in-depth documentation of all peripherals and modules available for the AVR XMEGA A Microcontroller family. All features are documented on a functional level and described in a general sense. All peripherals and modules ...

Page 3

Overview The XMEGA family of low power, high performance and peripheral rich CMOS 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instruc- tions in a single clock cycle, the XMEGA A achieves ...

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Block Diagram Figure 2-1. XMEGA A Block Diagram DACA PA[0..7] PORT A (8) ACA ADCA AREFA VCC/10 Int. Ref. Tempref AREFB ADCB ACB PB[0..7]/ JTAG PORT B (8) DACB IRCOM 8077H–AVR–12/09 PR[0..1] PQ[0..7] XTAL1 TOSC1 PP[0..7] PN[0..7] XTAL2 TOSC2 ...

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AVR CPU 3.1 Features • 8/16-bit high performance AVR RISC CPU – 138 instructions – Hardware multiplier • 32x8-bit registers directly connected to the ALU • Stack in RAM • Stack Pointer accessible in I/O memory space • Direct ...

Page 6

Figure 3-1. The Arithmetic Logic Unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated ...

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The SRAM holds data, and code cannot be executed from here. It can easily be accessed through the five different addressing modes supported in the AVR architecture. The first SRAM address is 0x2000. Data address 0x1000 to 0x1FFF is reserved ...

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When an enabled interrupt occurs, the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine. Hardware clears the corresponding interrupt flag automatically. A flexible interrupt controller has dedicated control registers with an ...

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Status Register The Status Register (SREG) contains information about the result of the most recently executed arithmetic or logic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status ...

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Figure 3-4. Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. The Register File is located in a separate address space, so the registers are not ...

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RAMP and Extended Indirect Registers In order to access program memory or data memory above 64K bytes, the address or address pointer must be more than 16-bits. This is done by concatenating one register to one of the X-, ...

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Accessing 16-bits Registers The AVR data bus is 8-bit so accessing 16-bit registers requires atomic operations. These regis- ters must be byte-accessed using two read or write operations. When reading the high byte is buffered and when writing the ...

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Sequence for execution of protected SPM/LPM 1. The application code writes the signature for execution of protected SPM/LPM to the CCP register. 2. Within 4 instruction cycles, the application code must execute the appropriate instruc- tion. The protected change ...

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This register is not available if the data memory including external memory is less than 64K bytes. Bit +0x08 Read/Write Initial Value • Bit 7:0 – RAMPD[7:0]: Extended Direct ...

Page 15

When accessing data addressees below 64K bytes, reading program memory locations below 64K bytes and writing program memory locations below 128K bytes, ...

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SPH - Stack Pointer Register High Bit +0x0E Read/Write Initial Value Note: • Bits 7:0 - SP[15:8]: Stack Pointer Register High byte These bits hold the 8 MSB of the 16-bits Stack Pointer (SP). 3.14.9 SREG - Status Register ...

Page 17

Bit 1 – Z: Zero Flag The Zero Flag (Z) indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag (C) ...

Page 18

Memories 4.1 Features • Flash Program Memory – One linear address space – In-System Programmable – Self-Programming and Bootloader support – Application Section for application code – Application Table Section for application code or data storage – Boot Section ...

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This prevents unrestricted access to the application software. A separate memory section contains the Fuse bytes. These are used for setting important sys- tem functions, and write access is only ...

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Application Section The Application section is the section of the Flash that is used for storing the executable applica- tion code. The protection level for the Application section can be selected by the Boot Lock Bits for this section. ...

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The Lock bits are used to set protection level on the different flash sections. They are used to block read and/or write access of the code. Lock bits can be written from en external program- mer and from the application ...

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Data Memory The Data memory contains the I/O Memory, internal SRAM, optionally memory mapped EEPROM and external memory if available. The data memory is organized as one continuous memory section, as shown in Figure 4-2. I/O Memory, EEPROM and ...

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EEPROM XMEGA has EEPROM memory for non-volatile data storage addressable either sep- arate data space (default can be memory mapped and accessed in normal data space. The EEPROM memory supports both byte ...

Page 24

Figure 4-3. 4.10.1 Bus Priority When several masters request access to the same bus, the bus priority is in the following order (from higher to lower priority) 1. Bus Master with ongoing access 2. Bus Master with ongoing burst a. ...

Page 25

As long as JTAG is disabled the I/O pins required for JTAG can be used as normal I/O pins. 4.14 IO Memory Protection Some features in the device is regarded to be critical for safety in ...

Page 26

DATA2 - Non-Volatile Memory Data Register Byte 2 The DATA2, DATA1 and ADDR0 registers represents the 24-bit value DATA. Bit +0x06 Read/Write Initial Value • Bit 7:0 - DATA[23:16]: NVM Data Register 2 This register gives the data value ...

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CTRLA - Non-Volatile Memory Control Register A Bit +0x0B Read/Write Initial Value • Bit 7:1 - Reserved Bits These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when ...

Page 28

INTCTRL - Non-Volatile Memory Interrupt Control Register Bit +0x0D Read/Write Initial Value • Bit 7:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this ...

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Bit 5:2 - Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 1 - EELOAD: EEPROM Page Buffer ...

Page 30

Register Description – Fuses and Lockbits 4.16.1 FUSEBYTE0 - Non-Volatile Memory Fuse Byte 0 - JTAG User ID Bit +0x00 Read/Write Initial Value • Bit 7 - JTAGUID[7:0]: JTAG USER ID These fuses can be used to set the ...

Page 31

Bit 6 - BOOTRST: Boot Loader Section Reset Vector The BOOTRST fuse can be programmed so the Reset Vector is pointing to the first address in the Boot Loader Flash Section. In this case, the device will start executing ...

Page 32

Table 4-3. STARTUPTIME[1:0] • Bit 1 - WDLOCK: Watchdog Timer lock The WDLOCK fuse can be programmed to lock the Watchdog Timer configuration. When this fuse is programmed the Watchdog Timer configuration cannot be changed, and the Watchdog Timer cannot ...

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Bit 5:4 - BODACT[1:0]: BOD operation in active mode The BODACT fuse bits set the BOD operation mode when the device is in active and idle mode of operation. For details on the BOD and BOD operation modes refer ...

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Table 4-8. BLBB[1:0] • Bit 5:4 - BLBA[1:0]: Boot Lock Bit Application Section These bits indicate the locking mode for the Application Section. Even though the BLBA bits are writable, they can only be written to a stricter locking. Resetting ...

Page 35

Bit 3:2 - BLBAT[1:0]: Boot Lock Bit Application Table Section These bits indicate the locking mode for the Application Table Section. Even though the BLBAT bits are writable, they can only be written to a stricter locking. Resetting the ...

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Register Description - Production Signature Row 4.17.1 RCOSC2M - Internal 2 MHz Oscillator Calibration Register Bit +0x00 Read/Write Initial Value • Bit 7:0 - RCOSC2M[7:0]: Internal 2 MHz Oscillator Calibration Value This byte contains the oscillator calibration value for ...

Page 37

LOTNUM0 - Lot Number Register 0 LOTNUM0, LOTNUM1, LOTNUM2, LOTNUM3, LOTNUM4 and LOTNUM5 contains the LOT number for each device. Together with the wafer number and wafer coordinates this gives an unique identifier or serial number for the device. ...

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LOTNUM4 - Lot Number Register 4 Bit +0x0A Read/Write Initial Value • Bit 7:0 - LOTNUM4[7:0] - LOT Number Byte 4 This byte contains byte 4 of the LOT number for the device. 4.17.9 LOTNUM5 - Lot Number Register ...

Page 39

COORDX1 - Wafer Coordinate X Register 1 Bit +0x13 Read/Write Initial Value • Bit 7:0 - COORDX0[7:0] - Wafer Coordinate X Byte 1 This byte contains byte 1 of wafer coordinate X for the device. 4.17.13 COORDY0 - Wafer ...

Page 40

ADCACAL1 - ADCA Calibration Register 1 Bit +0x21 Read/Write Initial Value • Bit 7:0 - ADCACAL1[7:0] - ADCA Calibration Byte 1 This byte contains byte 1 of the ADCA calibration data, and must be loaded into the ADCA CALH ...

Page 41

Bit 7:0 - TEMPSENSE0[7:0] - Temperature Sensor Calibration Byte 0 This byte contains the byte 0 (8 LSB) of the temperature measurement. 4.17.20 TEMPSENSE1 - Temperature Sensor Calibration Register 1 Bit +0x2F Read/Write Initial Value • Bit 7:0 - ...

Page 42

Bit 7:0 - DACAGAINCAL[7:0] - DACB Gain Calibration Byte This byte contains the gain calibration value for the Digital to Analog Converter B (DACB). Cali- bration of the Digital to Analog Converters are done during production test of the ...

Page 43

Bit 7:0 - DEVID0[7:0]: MCU Device ID Byte 1 This byte will always be read as 0x1E. This indicates that the device is manufactured by Atmel 4.20.2 DEVID1 - MCU Device ID Register 1 Bit +0x01 Read/Write Initial Value ...

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Bit 7:0 - JTAGUID[7:0]: JTAG User ID The JTAGUID can be used to identify two devices with identical Device JTAG scan chain. The JTAGUID will during reset automatically be loaded from flash and placed in these ...

Page 45

Configuration Change Protection mechanism, for details refer to ”Configuration Change Protection” on page 4.20.8 AWEXLOCK – Advanced Waveform Extension Lock Register Bit +0x09 Read/Write Initial Value • Bit 7:3 - Reserved These bits are reserved and will ...

Page 46

Register Summary - NVM Controller Address Name Bit 7 +0x00 ADDR0 +0x01 ADDR1 +0x02 ADDR2 +0x03 Reserved +0x04 DATA0 +0x05 DATA1 +0x06 DATA2 +0x07 Reserved +0x08 Reserved +0x09 Reserved +0x0A CMD +0x0B CTRLA +0x0C CTRLB +0x0D INTCTRL +0x0E Reserved ...

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Register Summary - Production Signature Row Address Auto Load Name +0x00 YES RCOSC2M +0x01 Reserved +0x02 YES RCOSC32K +0x03 YES RCOSC32M +0x04 Reserved +0x05 Reserved +0x06 Reserved +0x07 Reserved +0x08 NO LOTNUM0 +0x09 NO LOTNUM1 +0x0A NO LOTNUM2 +0x0B ...

Page 48

Register Summary - General Purpose I/O Registers Address Name Bit 7 +0x00 GPIOR0 +0x01 GPIOR1 +0x02 GPIOR2 +0x03 GPIOR3 +0x04 GPIOR4 +0x05 GPIOR5 +0x06 GPIOR6 +0x07 GPIOR7 +0x08 GPIOR8 +0x09 GPIOR9 +0x0A GPIOR10 +0x0B GPIOR11 +0x0C GPIOR12 +0x0D GPIOR13 ...

Page 49

DMA - Direct Memory Access Controller 5.1 Features • The DMA Controller allows high-speed transfers with minimal CPU intervention – from one memory area to another – from memory area to peripheral – from peripheral to memory area – ...

Page 50

DMA Transaction A complete DMA read and write operation between memories and/or peripherals is called a DMA transaction. A transaction is done in data blocks and the size of the transaction (number of bytes to transfer) is selectable from ...

Page 51

By default, a trigger starts a block transfer operation. The transfer continues until one block is transferred. When the block is transferred, the channel will wait for the next trigger to arrive before it start transferring the next block. It ...

Page 52

Error detection The DMA controller can detect erroneous operation. Error conditions are detected individually for each DMA channel, and the error conditions are: • Write to memory mapped EEPROM memory locations. • Reading EEPROM memory when the EEPROM is ...

Page 53

Register Description – DMA Controller 5.13.1 CTRL - DMA Control Register Bit +0x00 Read/Write Initial Value • Bit 7 - ENABLE: DMA Enable Setting this bit enables the DMA Controller. If the DMA Controller is enabled and this bit ...

Page 54

INTFLAGS - DMA Interrupt Status Register Bit +0x04 Read/Write Initial Value • Bit 7:4 - CHnERRIF[3:0]: DMA Channel n Error Interrupt Flag If an error condition is detected on DMA channel n, the CHnERRIF flag will be set. Writing ...

Page 55

TEMPL - DMA Temporary Register Low Bit +0x06 Read/Write Initial Value • Bit 7:0 - TEMP[7:0]: DMA Temporary Register 0 This register is used when reading 24- and 16-bit registers in the DMA controller. Byte 1 of the 16/24-bit ...

Page 56

Bit 2 - SINGLE: DMA Channel Single Shot Data transfer Setting this bit enables the single shot mode. The channel will then do a burst transfer of BURSTLEN bytes on the transfer trigger. This bit can not be changed ...

Page 57

Bit [3:2] - ERRINTLVL[1:0]: DMA Channel Error Interrupt Level These bits enable the interrupt for DMA channel transfer error select the interrupt level as described in 123. The enabled interrupt will trigger for the conditions when the ERRIF is ...

Page 58

Table 5-6. DESTRELOAD[1:0] • Bit 1:0 - DESTDIR[1:0]: DMA Channel Destination Address Mode These bits decide the DMA channel destination address mode according to 58. These bits can not be changed if the channel is busy. Table 5-7. DESTDIR[1:0] 5.14.4 ...

Page 59

Table 5-8. TRIGSRC base value Table 5-9. TRGSRC offset value 8077H–AVR–12/09 DMA Trigger Sources, base value for all modules and peripherals Group Configuration 0x00 OFF 0x01 SYS 0x10 ADCA 0x15 DACA 0x20 ADCB 0x25 DACB 0x40 TCC0 0x46 TCC1 0x4A ...

Page 60

Table 5-10. TRGSRC offset value Notes: Table 5-11. TRGSRC offset value Note: Table 5-12. TRGSRC offset value The Group Configuration is the “base_offset”, for example TCC1_CCA for the Timer/Counter C1 CC Channel A the transfer trigger. 5.14.5 TRFCNTH - DMA ...

Page 61

Bit 7:0 - TRFCNT[15:8]: DMA Channel n Block Transfer Count Register High byte These bits hold the 8 MSB of the 16-bits block transfer count. The default value of this register is 0x1 user write 0x0 to ...

Page 62

Bit 7:0 - SRCADDR[23:16]: DMA Channel Source Address 2 These bits hold byte 2 of the 24-bits source address. 5.14.9 SRCADDR1 - DMA Channel Source Address 1 Bit +0x09 Read/Write Initial Value • Bit 7:0 - SRCADDR[15:8]: DMA Channel ...

Page 63

Bit 7:0 - DESTADDR[15:8]: DMA Channel Destination Address 1 These bits hold byte 1 of the 24-bits source address. 5.14.13 DESTADDR0 - DMA Channel Destination Address 0 Bit +0x0C Read/Write Initial Value • Bit 7:0 - DESTADDR[7:0]: DMA Channel ...

Page 64

Register Summary – DMA Controller Address Name Bit 7 +0x00 CTRL ENABLE +0x01 Reserved - +0x02 Reserved - +0x03 INTFLAGS CH3ERRIF +0x04 STATUS CH3BUSY +0x05 Reserved - +0x06 TEMPL +0x07 TEMPH +0x10 CH0 Offset +0x20 CH1 Offset +0x30 CH2 ...

Page 65

Event System 6.1 Features • Inter peripheral communication and signalling • CPU and DMA independent operation • 8 Event Channels allows for signals to be routed at the same time • 100% predictable timing between peripherals ...

Page 66

Figure 6-1. The CPU is not part of the Event System, but it indicates that it is possible to manually generate events from software or by using the on-chip debug system. The Event System works in active and idle mode. ...

Page 67

Events can be manually generated by writing to the STROBE and DATA registers. 6.3.1 Signaling Events Signaling events are the most basic type of events. A signaling event does not contain any infor- mation apart from the indication of a ...

Page 68

Figure 6-3. Having eight multiplexers means that it is possible to route up to eight events at the same time also possible to route one event through several multiplexers. Not all XMEGA parts contain all peripherals. This only ...

Page 69

Event Timing An event normally lasts for one peripheral clock cycle, but some event sources, such as low level on an I/O pin, will generate events continuously. Details on this are described in the datasheet for each peripheral, but ...

Page 70

Figure 6-4. Figure 6-4 QDPH90 are the two quadrature signals. When QDPH90 leads QDPH0, the rotation is defined as positive or forward. When QDPH0 leads QDPH90, the rotation is defined as negative, or reverse. The concatenation of the two phase ...

Page 71

Set the period register of the Timer/Counter to ('line count 1). (The line count of the quadrature encoder). • Enable the Timer/Counter by setting CLKSEL to a CLKSEL_DIV1. The angle of a quadrature encoder attached to ...

Page 72

Table 6-3. CHnMUX[7:4] 0001 0010 0010 0010 0011 0100 0101 0101 0110 0110 0111 0111 1000 1001 1010 1011 1100 1100 1101 1101 1110 1110 1111 1111 Note: Table 6-4. T/C Event ...

Page 73

CHnCTRL – Event Channel n Control Register . Bit Read/Write Initial Value • Bit 7 - Reserved This bit is reserved and will always be read as zero. For compatibility with future devices, always write this bit to zero ...

Page 74

Table 6-6. DIGFILT[2:0] 6.8.3 STROBE – Event Strobe Register If the STROBE register location is written, each event channel will be set according to the STROBE[n] and corresponding DATA[n] bit setting if any are unequal to zero. A single event ...

Page 75

Register Summary Address Name Bit 7 +0x00 CH0MUX +0x01 CH1MUX +0x02 CH2MUX +0x03 CH3MUX +0x04 CH4MUX +0x05 CH5MUX +0x06 CH6MUX +0x07 CH7MUX +0x08 CH0CTRL - +0x09 CH1CTRL - +0x0A CH2CTRL - +0x0B CH3CTRL - +0x0C CH4CTRL - +0x0D CH5CTRL ...

Page 76

System Clock and Clock options 7.1 Features • Fast start-up time • Safe run-time clock switching • Internal Oscillators: – 32 MHz run-time calibrated RC oscillator – 2 MHz run-time calibrated RC oscillator – 32.768 kHz calibrated RC oscillator ...

Page 77

Figure 7-1. The Clock system, clock sources and clock distribution Real Time Counter clk rtc Brown-out Watchdog Detection Timer 32 kHz Int. ULP 7.3 Clock Distribution Figure 7-1 on page 77 7.3.1 System Clock - clk SYS The System Clock ...

Page 78

Peripheral Clock - clk The majority of peripherals and system modules use the Peripheral Clock. This includes the DMA Controller, Event System, Interrupt Controller, External Bus Interface and RAM. This clock is always synchronous to the CPU Clock but ...

Page 79

MHz Run-time Calibrated Internal Oscillator This RC oscillator provides an approximate 2 MHz clock. The oscillator employs a Digital Fre- quency Looked Loop (DFLL) that can be enabled for automatic run-time calibration of the oscillator. A factory-calibrated value ...

Page 80

System Clock, RTC and as the DFLL reference. Figure 7-4. Two capacitors, C1 and C2, may be added to match the required load capacitance for the con- nected ...

Page 81

The System Clock selection and prescaler registers are protected by the Configuration Change Protection mechanism, employing a timed write procedure for changing the system clock and prescaler settings. For details refer to 7.6 PLL with 1-31x Multiplication Factor A built-in ...

Page 82

Figure 7-6. TOSC1 TOSC2 When the DFLL is enabled it will count each oscillator clock cycle, and for each reference clock edge, the counter value is compared to the fixed ideal relationship between the reference clock and the 1kHz reference ...

Page 83

System Clock (i.e clock reference for the PLL when this is used as the active system clock) and an clock or oscillator fails (stops), the device will: • Switch to the 2 ...

Page 84

Register Description - Clock 7.9.1 CTRL - System Clock Control Register Bit +0x00 Read/Write Initial Value • Bit 7:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits ...

Page 85

Bit 6:2 - PSADIV[4:0]: Prescaler A Division Factor These bits define the division ratio of the clock prescaler A according to can be written run-time to change the clock frequency of the clk clock, clk Table 7-2. PSADIV[4:0] • ...

Page 86

LOCK - Clock System Lock Register Bit +0x02 Read/Write Initial Value • Bit 7:1 - Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to zero when ...

Page 87

Bit 0 - RTCEN: RTC Clock Source Enable Setting the RTCEN bit enables the selected clock source for the Real Time Counter. 7.10 Register Description - Oscillator 7.10.1 CTRL - Oscillator Control Register Bit +0x00 Read/Write Initial Value • ...

Page 88

STATUS - Oscillator Status Register Bit +0x01 Read/Write Initial Value • Bit 7:5 - Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to zero when this ...

Page 89

Table 7-5. FRQRANGE[1:0] • Bit 5 - X32KLPM: Crystal Oscillator 32.768 kHz Low Power Mode Setting this bit enables low power mode for the 32.768 kHz Crystal Oscillator. This will reduce the swing on the TOSC2 pin. • Bit 4 ...

Page 90

Bit 7:2 - Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 1 - XOSCFDIF: Failure Detection Interrupt ...

Page 91

Table 7-7. CLKSRC[1:0] Notes: • Bit 5 - Reserved This bit is reserved and will always be read as zero. For compatibility with future devices, always write this bit to zero when this register is written. • Bit 4:0 - ...

Page 92

Register Description - DFLL32M/DFLL2M 7.11.1 CTRL - DFLL Control Register Bit +0x00 Read/Write Initial Value • Bit 7:1 - Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these ...

Page 93

Bit 4:0 - CALH[12:8]: DFLL Calibration bits These bits hold the 6 Most Significant Bits (MSB) of the calibration value for the oscillator. A fac- tory-calibrated value is loaded from the signature row of the device and written to ...

Page 94

Register Summary - Clock Address Name Bit 7 +0x00 CTRL – +0x01 PSCTRL – +0x02 LOCK – +0x03 RTCCTRL – +0x04 Reserved – +0x05 Reserved – +0x06 Reserved – +0x07 Reserved – 7.13 Register Summary - Oscillator Address Name ...

Page 95

Power Management and Sleep 8.1 Features • 5 sleep modes – Idle – Power-down – Power-save – Standby – Extended standby • Power Reduction register to disable clock to unused peripherals 8.2 Overview XMEGA provides various sleep modes and ...

Page 96

Table 8-1 on page 96 and wake-up sources. Table 8-1. Sleep modes Idle Power-down Power-save Standby Extended Standby The wake-up time for the device is dependent on the sleep mode and the main clock source. The start-up time for the ...

Page 97

Standby Mode Standby mode is identical to Power-down with the exception that the enabled system clock sources are kept running, while the CPU, Peripheral and RTC clocks are stopped. This reduces the wake-up time. 8.3.5 Extended Standby Mode Extended ...

Page 98

Table 8-2. SMODE[2:0] • Bit 1 - SEN: Sleep Enable This bit must be set to make the MCU enter the selected sleep mode when the SLEEP instruc- tion is executed. To avoid unintentional entering of sleep modes ...

Page 99

PRPA/B - Power Reduction Port A/B Register Bit +0x01/+0x02 Read/Write Initial Value Note: • Bit 7:3 - Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to ...

Page 100

Bit 3 - SPI: Serial Peripheral Interface Setting this bit stops the clock to the SPI. When the bit is cleared the peripheral should be reini- tialized to ensure proper operation. • Bit 2 - HIRES: Hi-Resolution Extension Setting ...

Page 101

Register Summary - Sleep Address Name Bit 7 +0x00 CTRL - +0x01 Reserved - +0x02 Reserved - +0x03 Reserved - +0x04 Reserved - +0x05 Reserved - +0x06 Reserved - +0x07 Reserved - 8.8 Register Summary - Power Reduction Address ...

Page 102

Reset System 9.1 Features • Power-on reset source • Brown-out reset source • Software reset source • External reset source • Watchdog reset source • Program and Debug Interface reset source 9.2 Overview The Reset System will issue a ...

Page 103

Figure 9-1. 8077H–AVR–12/09 Reset system overview Reset Status Register Power - On Detection Reset Brown - Out Detection Reset External Reset Program and Debug Interface Reset Watchdog Reset Software Reset XMEGA A Reset Delay Counter Oscillator Startup Oscillator Calibration Counter ...

Page 104

Reset Sequence Reset request from any reset source immediately reset the device, and keep it in reset as long as the request is active. When all reset requests are released, the device will go through three stages before the ...

Page 105

The Brown-out detection (BOD) must be enabled to ensure safe operation and detect if V Only the Power-on reset Flag will be set after Power-on reset. The Brown-out Reset Flag is not set ...

Page 106

Brown-Out Detection The Brown-Out Detection (BOD) circuit monitors that the V trigger level, V low the trigger level for a minimum time, t above the trigger level again. Figure 9-4. For characterization data programmable BODLEVEL ...

Page 107

Sampled: In this mode the BOD circuit will sample the VCC level with a period identical to the 1 kHz output from the Ultra Low Power (ULP) oscillator. Between each sample the BOD is turned off. This mode will ...

Page 108

Figure 9-6. For information on configuration and use of the WDT, refer to the Timer” on page 9.4.5 Software reset The Software reset makes it possible to issue a system reset from software by writing to the Software Reset bit ...

Page 109

Register Description 9.5.1 STATUS - Reset Status Register Bit +0x00 Read/Write Initial Value • Bit 7 – 6: Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits ...

Page 110

Register Summary Address Name Bit 7 +0x00 STATUS – +0x01 CTRL – 8077H–AVR–12/09 Bit 6 Bit 5 Bit 4 Bit 3 – SRF PDIRF WDRF – – – XMEGA A Bit 2 Bit 1 Bit 0 BORF EXTRF PORF ...

Page 111

Battery Backup System 10.1 Features • Battery Backup voltage supply from dedicated V – One Ultra Low-power 32-bit Real Time Counter – One 32.768 kHz crystal oscillator with failure detection monitor – Two Battery Backup Registers • Automatic switching ...

Page 112

Battery Backup Module Figure 10-1. Battery Backup Module and its power domain implementation VBAT TOSC1 TOSC2 The Battery Backup Module consists of the following: • BAT backup battery power domain. It includes – A Battery Backup Power-On ...

Page 113

The the 32-kHz crystal oscillator, oscillator failure detection and Real Time Counter must be enabled from software before they can be used. 10.3.2 Battery Backup Brown-Out Detection The Battery Backup Brown-Out Detector (BBBOD) ensures detection of falling power in the ...

Page 114

Set the ACCEN bit and apply a RESET 1. Enable the Crystal oscillator. 2. Wait until Crystal Oscillator ready flag is set. 3. Enable XOSC Fault Detection. 4. Configure and enable the RTC32. 10.6 Register Description 10.6.1 CTRL: Battery ...

Page 115

These bits are protected by the Configuration Change Protection mechanism, for detailed description refer to 10.6.2 STATUS: Battery Backup Status Register Bit +0x01 Read/Write Reset Value • Bit 7 - BBPWR: Battery Backup Power The Power on the V BBPWR ...

Page 116

Bit [7:0] - BACKUP0: Battery Backup Register 0 This register can be used to store data in the Battery Backup Module before the main power is lost or removed. 10.6.4 BACKUP1: Battery Backup Register 1 Bit +0x03 Read/Write Reset ...

Page 117

WDT – Watchdog Timer 11.1 Features • 11 selectable timeout period, from • Two operation modes – Standard mode – Window mode • Runs from 1 kHz Ultra Low Power clock reference • Configuration lock ...

Page 118

Window Mode Operation In window mode operation the WDT uses two different timeout periods, a "closed" window time- out period (TO defines a duration from where the WDT cannot be reset: if the WDT is ...

Page 119

Registers Description 11.7.1 CTRL – Watchdog Timer Control Register Bit +0x00 Read/Write (unlocked) Read/Write (locked) Initial Value (x = fuse) • Bits 7:6 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, ...

Page 120

Bit 1 - ENABLE: Watchdog Enable This bit enables the WDT. In order to change this bit the CEN bit in 119 must be written to one at the same time. This bit is protected by the Configuration Change ...

Page 121

Table 11-2. WPER[3:0] 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 • Bit 1 - WEN: Watchdog Window Mode Enable This bit enables the Watchdog Window Mode. In order to change this bit the WCEN bit in ”WINCTRL ...

Page 122

Register Summary Address Name Bit 7 +0x00 CTRL - +0x01 WINCTRL - +0x02 STATUS - 8077H–AVR–12/09 Bit 6 Bit 5 Bit 4 Bit 3 - PER[3:0] - WPER[3: XMEGA A Bit 2 Bit 1 Bit 0 ...

Page 123

Interrupts and Programmable Multi-level Interrupt Controller 12.1 Features • Separate interrupt vector for each interrupt • Short, predictable interrupt response time • Programmable Multi-level Interrupt Controller – 3 programmable interrupt levels – Selectable priority scheme within low level interrupts ...

Page 124

The RET (subroutine return) instruction cannot be used when returning from the inter- rupt handler routine, as this will not return the PMIC to its right state. 12.4 Interrupts All interrupts and the reset vector each have a separate ...

Page 125

In addition the response time is increased by the start-up time from the selected sleep mode. A return from an interrupt handling routine takes five clock cycles. During these five ...

Page 126

Figure 12-1. Static priority. 12.6.2 Round-robin scheduling To avoid the possible starvation problem for low level interrupts with static priority, the PMIC gives the possibility for round-robin scheduling for low level interrupts. When round-robin sched- uling is enabled, the interrupt ...

Page 127

Moving Interrupts Between Application and Boot Section The interrupt vectors can be moved from the default location in the Application Section in Flash to the start of the Boot Section. 12.8 Register Description 12.8.1 STATUS - PMIC Status Register ...

Page 128

This register is not reinitialized to its initial value if round-robing scheduling is disabled default static priority is needed the register must be written to zero. 12.8.3 CTRL - PMIC Control Register Bit +0x02 ...

Page 129

I/O Ports 13.1 Features • Selectable input and output configuration for each pin individually • Flexible pin configuration through dedicated Pin Configuration Register • Synchronous and/or asynchronous input sensing with port interrupts and events • Asynchronous wake-up signalling • ...

Page 130

Figure 13-1. General I/O pin functionality. 13.3 Using the I/O Pin Use of an I/O pin is controlled from the user software. Each port has one Data Direction (DIR), Data Output Value (OUT) that is used for port pin control. ...

Page 131

I/O Pin Configuration The Pin n Configuration (PINnCTRL) register is used for additional I/O pin configuration. A pin can be set in a totem-pole, wired-AND, or wired-OR configuration also possible to enable inverted input and output for ...

Page 132

Totem-pole with Pull-up In this mode, the configuration is as for Totem-pole, expect the pin is configured with internal pull-up when set as input. Figure 13-4. I/O pin configuration - Totem-pole with pull-up (on input). 13.4.2 Bus-keeper When the ...

Page 133

Figure 13-6. Output configuration - Wired-OR with optional pull-down. 13.4.4 Wired-AND With Wired-AND configuration, the pin will be driven low when the corresponding bit in OUT is written to zero. When OUT is set to one, the pin is released ...

Page 134

Figure 13-8. Synchronization when reading an externally applied pin value. 13.6 Input Sense Configuration Input sensing is used to detect an edge or level on the I/O pin input. The different sense configu- rations that are available for each pin ...

Page 135

Port Interrupt Each port has two interrupt vectors, and it is configurable which pins on the port that can be used to trigger each interrupt request. Port interrupts must be enabled before they can be used. Which sense configurations ...

Page 136

Table 13-3. Sense settings Rising edge Falling edge Both edges Low level 13.8 Port Event Port pins can generate an event when there is a change on the pin. The sense configurations decide when each pin will generate events. Event ...

Page 137

Figure 13-10. Port override signals and related logic 13.10 Slew-rate Control Slew-rate control can be enabled for all I/O pins individually. Enabling the slew rate limiter will typically increase the rise/fall time by 50-150% depending on voltage, temperature and load. ...

Page 138

Normally this is one peripheral clock cycle only. 13.12 Multi-configuration MPCMASK can be used to set a bit mask for the pin configuration registers. When setting bit n ...

Page 139

DIRCLR - Data Direction Clear Register Bit +0x02 Read/Write Initial Value • Bit 7:0 - DIRCLR[7:0]: Port Data Direction Clear This register can be used instead of a Read-Modify-Write to set individual pins as input. Writing a one to ...

Page 140

Bit 7:0 - OUTSET[7:0]: Data Output Value Set This register can be used instead of a Read-Modify-Write to set the output value on individual pins to one. Writing a one to a bit will set the corresponding bit in ...

Page 141

INTCTRL - Interrupt Control Register Bit +0x09 Read/Write Initial Value • Bit 7:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is ...

Page 142

INTFLAGS - Interrupt Flag Register Bit +0x0C Read/Write Initial Value • Bit 7:2 - Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to zero when this ...

Page 143

Bit 2:0 - ISC[2:0]: Input/Sense Configuration These bits set the input and sense configuration on pin n according to configuration decides how the pin can trigger port interrupts and events. When the input buffer is not disabled, the schmitt ...

Page 144

Bit 7:4 - VP1MAP: Virtual Port 1 Mapping These bits decide which ports should be mapped to Virtual Port 1. The registers DIR, OUT, IN and INTFLAGS will be mapped. Accessing the virtual port registers is equal to accessing ...

Page 145

Table 13-6. VPnMAP[3:0] 13.15.4 CLKEVOUT - Clock and Event Out Register Bit +0x04 Read/Write Initial Value • Bit 7:6 - Reserved These bits are reserved and will always be read as one. For compatibility with future devices, always write these ...

Page 146

Table 13-8. CLKOUT[1: 13.16 Register Description – Virtual Port 13.16.1 DIR - Data Direction Bit +0x00 Read/Write Initial Value • Bit 7:0 - DIR[7:0]: Data Direction Register This register sets the data direction for the individual ...

Page 147

Bit 7:0 - IN[7:0]: Data Input Value This register shows the value present on the pins if the digital input buffer is enabled. The config- uration of "VPCTRLA - Virtual Port-map Control Register A" or "VPCTRLB - Virtual Port-map ...

Page 148

Register Summary – Ports Address Name Bit 7 +0x00 DIR +0x01 DIRSET +0x02 DIRCLR +0x03 DIRTGL +0x04 OUT +0x05 OUTSET +0x06 OUTCLR +0x07 OUTTGL +0x08 IN +0x09 INTCTRL - +0x0A INT0MASK +0x0B INT1MASK +0x0C INTFLAGS - +0x0D Reserved - ...

Page 149

TC - 16-bit Timer/Counter 14.1 Features • 16-bit Timer/Counter • Double Buffered Timer Period Setting • Combined Compare or Capture (CC) Channels ( and D) • All Compare or Capture Channels are Double Buffered ...

Page 150

Figure 14-1. 16-bit Timer/Counter and Closely Related Peripheral Timer/Counter Base Counter Timer Period Compare/Capture Channel B Compare/Capture Channel A Comparator The Timer/Counter consists of a Base Counter and a set of Compare or Capture (CC) channels. The Base Counter can ...

Page 151

Definitions The following definitions are used extensively throughout the Timer/Counter documentation: Table 14-1. Name BOTTOM MAX TOP UPDATE In general the term Timer is used when the Timer/Counter clock control is handled by an internal source and the term ...

Page 152

Figure 14-2. Timer/Counter Block Diagram Bus Bridge The Counter Register (CNT), the Period Registers w/buffer (PER and PERBUF), and the com- pare and Capture registers w/buffers (CCx and CCxBUF) are 16-bit registers. During normal operation the counter value is continuously ...

Page 153

Clock and Event Sources The Timer/Counter can be clocked from the Peripheral Clock (clk tem, and Figure 14-3. Clock and Event Selection clk The Peripheral Clock is fed into the Common Prescaler (common for all Timer/Counters in a device). ...

Page 154

Figure 14-4. Period and Compare Double Buffering When the CC channels is used for capture operation a similar Double buffering mechanism is used, but the Buffer Valid flag is set on the capture event as shown in the buffer and ...

Page 155

Normal Operation In Normal Operation the Counter will count in the direction set by the Direction (DIR) bit for each clock until it reaches TOP or BOTTOM. When TOP is reached when up-counting, the counter will be set to ...

Page 156

Figure 14-7. Changing The Period without Buffering CNT When double buffering is used, the buffer can be written at any time, but the Period Register is always updated on the “update” condition as shown in and generation of odd waveforms. ...

Page 157

Event Source Selection for capture operation The Event Action setting in the Timer/Counter will determine the type of capture that is done. The CC channel to use must be enabled individually before capture can be done. When the cap- ture ...

Page 158

Frequency Capture Selecting the frequency capture event action, makes the enabled capture channel perform an input capture and restart on positive edge events. This enables Timer/Counter to use capture to measure the period or frequency of a signal directly. ...

Page 159

Figure 14-11. Pulse-width capture of external signal. external signal events CNT 14.7.4 32-bit Input Capture Two Timer/Counters can be used together to enable true 32-bit Input Capture typical 32-bit Input Capture setup the overflow event of the least ...

Page 160

Waveform Generation The compare channels can be used for waveform generation on the corresponding port pins. To make the waveform visible on the connected port pin, the following requirements must be fulfilled waveform generation mode must be ...

Page 161

Figure 14-13. Single slope Pulse Width Modulation CNT WG Output The PER register defines the PWM resolution. The minimum resolution is 2-bit (PER=0x0003), and maximum resolution is 16-bit (PER=MAX). The following equation can be used for calculate the exact resolution ...

Page 162

Figure 14-14. Dual-slope Pulse Width Modulation CNT WG Output Using dual-slope PWM result in a lower maximum operation frequency compared to the single- slope PWM operation. The period register (PER) defines the PWM resolution. The minimum resolution is 2-bit (PER=0x0003), ...

Page 163

Figure 14-15. Port override for Timer/Counter 0 and 1 14.9 Interrupts and events The T/C can generate both interrupts and events. The Counter can generate an interrupt on overflow/underflow, and each CC channel has a separate interrupt that is used ...

Page 164

DMA Support. The interrupt flags can be used to trigger DMA transactions. transfer triggers available from the T/C, and the DMA action that will clear the transfer trigger. For more details on using DMA refer to Table 14-2. Request ...

Page 165

Register Description 14.12.1 CTRLA - Control Register A Bit +0x00 Read/Write Initial Value • Bit 7:4 - Reserved bits These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero ...

Page 166

Bit 3 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. • Bit 2:0 – WGMODE[2:0]: Waveform Generation Mode These bits ...

Page 167

CTRLD - Control Register D Bit +0x03 Read/Write Initial Value • Bit 7:5 – EVACT[2:0]: Event Action These bits define the Event Action the timer will perform on an event according to page 167. The EVSEL setting will decide ...

Page 168

Table 14-6. EVSEL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1xxx 14.12.5 CTRLE - Control Register E Bit +0x04 Read/Write Initial Value • Bit 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with ...

Page 169

Bit 3:2 - ERRINTLVL[1:0]:Timer Error Interrupt Level These bits enable the Timer Error Interrupt and select the interrupt level as described in rupts and Programmable Multi-level Interrupt Controller” on page • Bit 1:0 - OVFINTLVL[1:0]:Timer Overflow/Underflow Interrupt Level These ...

Page 170

Bit 3:2 - CMD[1:0]: Timer/Counter Command These command bits can be used for software control of update, restart, and reset of the Timer/Counter. The command bits are always read as zero. Table 14-7. CMD • ...

Page 171

INTFLAGS - Interrupt Flag Register Bit +0x0C Read/Write Initial Value • Bit 7:4 - CCxIF: Compare or Capture Channel x Interrupt Flag The Compare or Capture Interrupt Flag (CCxIF) is set on a compare match input ...

Page 172

For more details refer to Bit +0x0F Read/Write Initial Value 14.12.12 CNTH - Counter Register H The CNTH and CNTL register pair represents the 16-bit value CNT. CNT contains the 16-bit counter value in the Timer/Counter. The CPU and DMA ...

Page 173

PERL - Period Register L Bit +0x26 Read/Write Initial Value • Bit 7:0 - PER[7:0] These bits holds the 8 LSB of the 16-bit Period register. 14.12.16 CCxH - Compare or Capture Register n H The CCxH and CCxL ...

Page 174

Bit +0x37 Read/Write Initial Value • Bit 7:0 - PERBUF[15:8] These bits holds the 8 MSB of the 16-bit Period Buffer register. 14.12.19 PERBUFL - Timer/Counter Period Buffer L Bit +0x36 Read/Write Initial Value • Bit 7:0 - PERBUF[7:0] These ...

Page 175

Register Summary Address Name Bit 7 +0x00 CTRLA +0x01 CTRLB CCDEN +0x02 CTRLC - +0x03 CTRLD +0x04 CTRLE - +0x05 Reserved - +0x06 INTCTRLA - +0x07 INTCTRLB CCCINTLVL[1:0] +0x08 CTRLFCLR - +0x09 CTRLFSET - +0x0A CTRLGCLR - +0x0B CTRLGSET ...

Page 176

AWeX – Advanced Waveform Extension 15.1 Features • 4 Dead-Time Insertion (DTI) Units (8-pin) – 8-bit Resolution – Separate High and Low Side Dead-Time Setting – Double Buffered Dead-Time – Halts Timer During Dead-Time (Optional) • Event Controlled Fault ...

Page 177

The Pattern Generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In addition, the waveform generator output from the Compare Channel A can be distributed to and override all the port ...

Page 178

Figure 15-2. Timer/Counter extensions and port override logic 8077H–AVR–12/ hannel hannel W G ...

Page 179

Dead Time Insertion The Dead Time Insertion (DTI) unit enables generation of “off” time where both the non-inverted Low Side (LS) and inverted High Side (HS) of the WG output is low. This “off” time is called dead-time, and ...

Page 180

Figure 15-4. Dead Time Generator timing diagram "dti_cnt" "WG output" "dtls" "dths" 15.5 Pattern Generation The pattern generator extension reuses the DTI registers to produce a synchronized bit pattern on the port it is connected to. In addition, the waveform ...

Page 181

Fault Protection The Fault Protection feature enables fast and deterministic action when a fault is detected. The fault protection is event controlled, thus any event from the Event System can be used to trigger a fault action. When the ...

Page 182

Lock Register. For more details refer to Advanced Waveform Extension Lock Register” on page When the lock bit is set, the Control Register A, the Output Override Enable Register and the Fault Dedec.tion Event Mask register cannot be changed. To ...

Page 183

FDEMASK - Fault Detect Event Mask Register Bit +0x02 Read/Write Initial Value • Bit 7:0 - FDEVMASK[7:0]: Fault Detect Event Mask These bits enables the corresponding event channel as fault condition input source. Event from all event channels will ...

Page 184

Table 15-1. FDACT[1:0] 15.7.4 STATUS - Status Register Bit +0x04 Read/Write Initial Value • Bit 7:3 - Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to zero ...

Page 185

Bit 7:0 - DTBOTH: Dead-Time Both Sides Writing to this register will update both DTHS and DTLS registers at the same time (i.e. at the same I/O write access). 15.7.6 DTBOTHBUF - Dead-time Concurrent Write to Both Sides Buffer ...

Page 186

DTHSBUF - Dead-Time High Side Buffer Register Bit +0x0B Read/Write Initial Value • Bit 7:0 - DTHSBUF: Dead-Time High Side Buffer This register is the buffer for the DTHS Register. If double buffering is used, valid contents in this ...

Page 187

Register Summary Address Name Bit 7 +0x00 CTRL - +0x01 Reserved - +0x02 FDEMASK +0x03 FDCTRL - +0x04 STATUS - +0x05 Reserved - +0x06 DTBOTH +0x07 DTBOTHBUF +0x08 DTLS +0x09 DTHS +0x0A DTLSBUF +0x0B DTHSBUF +0x0C OUTOVEN 8077H–AVR–12/09 Bit ...

Page 188

Hi-Res - High Resolution Extension 16.1 Features • Increases Waveform Generator Resolution bits) • Supports Frequency generation, and single and dual-slope PWM operation • Supports Dead-Time Insertion (AWeX) • Supports Pattern Generation (AWeX) 16.2 Overview The ...

Page 189

Register Description 16.3.1 CTRLA - Hi-Res Control Register A Bit +0x00 Read/Write Initial Value • Bit 7:2 - Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits ...

Page 190

RTC - Real Time Counter 17.1 Features • 16-bit resolution • Selectable clock reference – 32.768 kHz – 1.024 kHz • Programmable prescaler • 1 Compare register • 1 Period register • Clear Timer on overflow • Optional Interrupt/ ...

Page 191

Clock domains The RTC is asynchronous, meaning it operates from a different clock source and independently of the main System Clock and its derivative clocks such as the Peripheral Clock. For Control and Count register updates it will take ...

Page 192

STATUS - Real Time Counter Status Register Bit +0x01 Read/Write Initial Value • Bits 7:1 - Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to zero ...

Page 193

INTFLAGS - RTC Interrupt Flag Register Bit +0x03 Read/Write Initial Value • Bits 7:2 - Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to zero when ...

Page 194

Bits 7:0 - CNT[15:8]: Real Time Counter value High byte These bits hold the 8 MSB of the 16-bit Real Time Counter value. 17.3.7 CNTL - Real Time Counter Register L Bit +0x08 Read/Write Initial Value • Bits 7:0 ...

Page 195

COMPH - Real Time Counter Compare Register H The COMPH and COMPL register pair represent the 16-bit value COMP. COMP is constantly compared with the counter value (CNT). A compare match will set the COMPIF in the INT- FLAGS ...

Page 196

Register Summary Address Name Bit 7 +0x00 CTRL - +0x01 STATUS - +0x02 INTCTRL - +0x03 INTFLAGS - +0x04 TEMP +0x08 CNTL +0x09 CNTH +0x0A PERL +0x0B PERH +0x0C COMPL +0x0D COMPH 17.5 Interrupt Vector Summary Table 17-2. RTC ...

Page 197

RTC32 - 32-bit Real Time Counter 18.1 Features • 32-bit resolution • Selectable clock reference – 1.024 kHz – • One Compare register • One Period register • Clear Timer on overflow • Optional Interrupt/ Event on ...

Page 198

Clock selection An external 32.768 kHz crystal oscillator must be used as clock source. Two different frequency outputs are available form this, and the RTC clock input can be 1.024 kHz or 1 Hz. 18.2.2 Clock domains The RTC ...

Page 199

Bit 0 - ENABLE: RTC Enable Setting this bit enables the RTC. The synchronization time between the RTC and the System Clock domains is one half RTC clock cycle from writing the register and until this has effect in ...

Page 200

Bits 1:0 - OVFINTLVL[1:0]: RTC Overflow Interrupt Enable These bits enable the RTC Overflow Interrupt and select the interrupt level as described in tion 12. ”Interrupts and Programmable Multi-level Interrupt Controller” on page interrupt will trigger when the OVFIF ...

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