ATxmega128A3 Atmel Corporation, ATxmega128A3 Datasheet - Page 124

• Manufacturer Part Number: ATxmega128A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A3

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

12.4
12.4.1
12.4.2
8077H–AVR–12/09
Interrupts
NMI – Non-Maskable Interrupts
Interrupt Response Time
request. The RET (subroutine return) instruction cannot be used when returning from the inter-
rupt handler routine, as this will not return the PMIC to its right state.
All interrupts and the reset vector each have a separate program vector address in the program
memory space. The lowest address in the program memory space is the reset vector. All inter-
rupts are assigned individual control bits for enabling and setting the interrupt level, and this is
set in the control registers for each peripheral that can generate interrupts. Details on each inter-
rupt are described in the peripheral where the interrupt is available.
All interrupts have an interrupt flag associated to it. When the interrupt condition is present, the
interrupt flag will be set, even if the corresponding interrupt is not enabled. For most interrupts,
the interrupt flag is automatically cleared when executing the interrupt vector. Writing a logical
one to the interrupt flag will also clear the flag. Some interrupt flags are not cleared when execut-
ing the interrupt vector, and some are cleared automatically when an associated register is
accessed (read or written). This is described for each individual interrupt flag.
If an interrupt condition occurs while another higher priority interrupt is executing or pending, the
interrupt flag will be set and remembered until the interrupt has priority. If an interrupt condition
occurs while the corresponding interrupt is not enabled, the interrupt flag will be set and remem-
bered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more
interrupt conditions occur while global interrupts are disabled, the corresponding interrupt flag
will be set and remembered until global interrupts are enabled. All pending interrupts are then
executed according to their order of priority.
Interrupts can be blocked when executing code from a locked section, e.g. when the Boot Lock
bits are programmed. This feature improves software security, refer to memory programming for
details on lock bit settings.
Interrupts are automatically disabled for up to 4 CPU clock cycles when the Configuration
Change Protection register is written with the correct signature, refer to
tion Change Protection” on page 12
Non-Maskable Interrupts (NMI) are hardwired. It is not selectable which interrupts represent NMI
and which represent regular interrupts. Non-Maskable Interrupts must be enabled before they
can be used. Refer to the device data sheet for NMI present on each the device.
A NMI will be executed regardless of the setting of the I-bit, and it will never change the I-bit. No
other interrupts can interrupt a NMI interrupt handler. If more than one NMI is requested at the
same time, priority is static according to interrupt vector address where lowest address has high-
est priority.
The interrupt response time for all the enabled interrupts is five CPU clock cycles minimum. Dur-
ing these five clock cycles the program counter is pushed on the stack. After five clock cycles,
the program vector for the interrupt is executed. The jump to the interrupt handler takes three
clock cycles.
If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed
before the interrupt is served. If an interrupt occurs when the device is in sleep mode, the inter-
for more details.
Section 3.12 ”Configura-
XMEGA A
124