ATxmega128D4 Atmel Corporation, ATxmega128D4 Datasheet - Page 199

• Manufacturer Part Number: ATxmega128D4
• Manufacturer: Atmel Corporation

Specifications of ATxmega128D4

• Flash (kbytes): 128 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Speed: No
• Usb Interface: No
• Spi: 4
• Twi (i2c): 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 200
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 14
• Input Capture Channels: 14
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

18. USART
18.1
18.2
8210B–AVR–04/10
Features
Overview
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The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication module. The USART supports full duplex communication,
and both asynchronous and clocked synchronous operation. The USART can be set in Master
SPI compliant mode and be used for SPI communication.
Communication is frame based, and the frame format can be customized to support a wide
range of standards. The USART is buffered in both direction, enabling continued data transmis-
sion without any delay between frames. There are separate interrupt vectors for receive and
transmit complete, enabling fully interrupt driven communication. Frame error and buffer over-
flow are detected in hardware and indicated with separate status flags. Even or odd parity
generation and parity check can also be enabled.
A block diagram of the USART is shown in
Clock Generator, the Transmitter and the Receiver, indicated in dashed boxes.
Full Duplex Operation (Independent Serial Receive and Transmit Registers)
Asynchronous or Synchronous Operation
Master or Slave Clocked Synchronous Operation
Enhanced Baud Rate Generator
Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
Odd or Even Parity Generation and Parity Check Supported by Hardware
Data OverRun and Framing Error Detection
Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
Multi-processor Communication Mode
Double Speed Asynchronous Communication Mode
Master SPI mode, Three-wire Synchronous Data Transfer
IRCOM Module for IrDA compliant pulse modulation/demodulation
– Supports all four SPI Modes of Operation (Mode 0, 1, 2, and 3)
– LSB First or MSB First Data Transfer (Configurable Data Order)
– Queued Operation (Double Buffered)
– High Speed Operation (f
XCK,max
= f
PER
/2)
Figure 18-1 on page
200. The main parts are the
XMEGA D
199