ATxmega192A3U Atmel Corporation, ATxmega192A3U Datasheet - Page 260

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ATxmega192A3U

Manufacturer Part Number
ATxmega192A3U
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega192A3U

Flash (kbytes)
192 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
16
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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21.3
8331A–AVR–07/11
General TWI Bus Concepts
The TWI provides a simple, bidirectional, two-wire communication bus consisting of a serial
clock line (SCL) and a serial data line (SDA). The two lines are open-collector lines (wired-AND),
and pull-up resistors (Rp) are the only external components needed to drive the bus. The pull-up
resistors provide a high level on the lines when none of the connected devices are driving the
bus
The TWI bus is a simple and efficient method of interconnecting multiple devices on a serial bus.
A device connected to the bus can be a master or slave, where the master controls the bus and
all communication.
Figure 21-1 on page 260
Figure 21-1. TWI bus topology.
A unique address is assigned to all slave devices connected to the bus, and the master will use
this to address a slave and initiate a data transaction.
Several masters can be connected to the same bus, called a multi-master environment. An arbi-
tration mechanism is provided for resolving bus ownership among masters, since only one
master device may own the bus at any given time.
A device can contain both master and slave logic, and can emulate multiple slave devices by
responding to more than one address.
A master indicates the start of a transaction by issuing a START condition (S) on the bus. An
address packet with a slave address (ADDRESS) and an indication whether the master wishes
to read or write data (R/W) are then sent. After all data packets (DATA) are transferred, the mas-
ter issues a STOP condition (P) on the bus to end the transaction. The receiver must
acknowledge (A) or not-acknowledge (A) each byte received.
Figure 21-2 on page 261
SDA
SCL
V
CC
R
P
R
P
illustrates the TWI bus topology.
shows a TWI transaction.
DEVICE #1
TWI
R
S
R
S
DEVICE #2
Atmel AVR XMEGA AU
TWI
R
S
R
S
Note: R
DEVICE #N
TWI
R
S
S
is optional
R
S
260

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