ATxmega64A4U Atmel Corporation, ATxmega64A4U Datasheet - Page 231

• Manufacturer Part Number: ATxmega64A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20. USB – Universal Serial Bus Interface
20.1
20.2
8331A–AVR–07/11
Features
Overview
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The USB module is a USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant
interface.
The USB supports 16 endpoint addresses. All endpoint addresses have one input and one out-
put endpoint, for a total of 31 configurable endpoints. Each endpoint address is fully configurable
and can be configured for any of the four transfer types: control, interrupt, bulk or isochronous.
The data payload size is also selectable, and it supports data payloads up to 1023bytes.
No dedicated memory is allocated for or included in the USB module. Internal SRAM is used to
keep the configuration for each endpoint address, and the data buffer for each endpoint. The
memory locations used for endpoint configurations and data buffers are fully configurable. The
amount of memory allocated is fully dynamic according to the number of endpoints in use, and
the configuration of these. The USB module has built-in Direct Memory Access (DMA) and will
read/write data from/to the SRAM when a USB transaction takes place.
USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface
Integrated on-chip USB transceiver, no external components needed
16 endpoint addresses with full endpoint flexibility for up to 31 endpoints
Endpoint address transfer type selectable to
Configurable data payload size per endpoint, up to 1023bytes
Endpoint configuration and data buffers located in internal SRAM
Built in Direct Memory Access (DMA) to internal SRAM for
Ping-Pong operation for higher throughput and double buffered operation
Multi-Packet transfer for reduced interrupt load and software intervention
Transaction Complete FIFO for work flow management when using multiple endpoints
Clock selection independent of system clock source and selection
Minimum 1.5MHz CPU clock required for low speed USB operation
Minimum 12MHz CPU clock required for full speed operation
Connection to event system
On chip debug possibilities during USB transactions
– One input endpoint per endpoint address
– One output endpoint per endpoint address
– Control transfers
– Interrupt transfers
– Bulk transfers
– Isochronous transfers
– Configurable location for endpoint configuration data
– Configurable location for each endpoint's data buffer
– Endpoint configurations
– Read and write endpoint data
– Input and output endpoint data buffers used in a single direction
– CPU/DMA Controller can update data buffer during transfer
– Data payload exceeding max packet size is transferred in one continuous transfer
– No interrupts or software interaction on packet transaction level
– Tracks all completed transactions in a first come, first serve work-queue
Atmel AVR XMEGA AU
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