ATxmega64A4U Atmel Corporation, ATxmega64A4U Datasheet - Page 416

• Manufacturer Part Number: ATxmega64A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32.4.2
32.4.3
32.4.3.1
32.4.4
8331A–AVR–07/11
Disabling
JTAG Instruction Set
Frame Format and Characters
The PDICOM Instruction
instruction is shifted into the JTAG instruction register, the JTAG interface can be used to
access the PDI for external programming and on-chip debugging.
The JTAG interface can be disabled by unprogramming the JTAGEN fuse or by setting the
JTAG disable bit in the MCU control register from the application code.
The Atmel XMEGA specific JTAG instruction set consist of eight instructions related to boundary
scan and PDI access for programming. For more details on JTAG and the general JTAG instruc-
tion set, refer to
When the PDICOM instruction is shifted into the JTAG instruction register, the 9-bit PDI commu-
nication register is selected as the data register. Commands are shifted into the register as
results from previous commands are shifted out from the register. The active TAP controller
states are (see
The JTAG physical layer supports a fixed frame format. A serial frame is defined to be one char-
acter of eight data bits followed by one parity bit.
Figure 32-10. JTAG serial frame format
Three special data characters are used. Common among these is that the parity bit is inverted in
order to force a parity error upon reception. The BREAK character (0xBB+P1) is used by the
external programmer to force the PDI to abort any ongoing operation and bring the PDI control-
ler into a known state. The DELAY character (0xDB+P1) is used by the PDI to tell the
programmer that it has no data ready. The EMPTY character (0xEB+P1) is used by the PDI to
tell the programmer that it has no transmission pending (i.e., the PDI is in RX-mode).
(0-7)
P
• Capture DR: Parallel data from the PDI controller is sampled into the PDI communication
• Shift DR: The PDI communication register is shifted by the TCK input
• Update DR: Commands or operands are parallel-latched into registers in the PDI controller
register
Data/command bits, least-significant bit sent first (0 to 7)
Parity bit, even parity used
”TAP - Test Access Port” on page
”JTAG Instructions” on page
0
1
2
405.
3
FRAME
403):
4
Atmel AVR XMEGA AU
5
6
7
P
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