AD9600 Analog Devices, AD9600 Datasheet - Page 23

• Manufacturer Part Number: AD9600
• Description: 10-Bit, 105 MSPS/125 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9600

• Resolution (bits): 10bit
• # Chan: 2
• Sample Rate: 150MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

THEORY OF OPERATION
The AD9600 dual ADC design can be used for diversity
reception of signals, where the ADCs are operating identically
on the same carrier but from two separate antennae. The ADCs
can also be operated with independent analog inputs. The user
can sample any f
using appropriate low-pass or band-pass filtering at the ADC
inputs with little loss in ADC performance. Although operation
of up to 450 MHz analog input is permitted, ADC distortion
increases at frequencies toward the higher end of this range.
In nondiversity applications, the AD9600 can be used as a
baseband receiver where one ADC is used for I input data and
the other used for Q input data.
Synchronization capability is provided to allow synchronized
timing among multiple channels or multiple devices.
Programming and control of the AD9600 is accomplished using
a 3-bit SPI-compatible serial interface.
ADC ARCHITECTURE
The AD9600 architecture consists of a dual front-end sample-
and-hold amplifier (SHA) followed by a pipelined switched-
capacitor ADC. The quantized outputs from each stage are
combined into a final 10-bit result in the digital correction
logic. The pipelined architecture permits the first stage to
operate on a new input sample while the remaining stages
operate on preceding samples. Sampling occurs on the rising
edge of the clock.
Each stage of the pipeline excluding the last consists of a low
resolution flash ADC connected to a switched-capacitor digital-
to-analog converter (DAC) and an interstage residue amplifier
(a multiplying digital-to-analog converter (MDAC)). The residue
amplifier magnifies the difference between the reconstructed
DAC output and the flash input for the next stage in the
pipeline. One bit of redundancy is used in each stage to
facilitate digital correction of flash errors. The last stage simply
consists of a flash ADC.
The input stage of each channel contains a differential SHA that
can be ac- or dc-coupled in differential or single-ended modes.
The output-staging block aligns the data, corrects errors, and
passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
go into a high impedance state.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9600 is a differential switched-
capacitor SHA that has been designed for optimum
performance while processing a differential input signal.
The clock signal alternatively switches the SHA between
sample mode and hold mode (see Figure 45). When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
S
/2 frequency segment from dc to 200 MHz
Rev. B | Page 23 of 72
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. A shunt capacitor can be placed
across the inputs to provide dynamic charging currents. This
passive network creates a low-pass filter at the ADC’s input;
therefore, the precise values are dependent on the application.
In undersampling (IF sampling) applications, any shunt capacitors
should be reduced. In combination with the driving source
impedance, the shunt capacitors limit the input bandwidth. See
the AN-742 Application Note, Frequency Domain Response of
Switched-Capacitor ADCs; the AN-827 Application Note, A
Resonant Approach to Interfacing Amplifiers to Switched-Capacitor
ADCs; and the Analog Dialogue article
Front-End for Wideband A/D
for more information. In general, the precise values are dependent
on the application.
For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched.
An internal differential reference buffer creates positive and neg-
ative reference voltages that define the input span of the ADC core.
The span of the ADC core is set by the buffer to 2 × VREF.
Input Common Mode
The analog inputs of the AD9600 are not internally dc-biased.
Therefore, in ac-coupled applications, the user must provide this
bias externally. Setting the device so that V
recommended for optimum performance, but the device can
function over a wider range with reasonable performance (see
Figure 44). An on-board common-mode voltage reference is
included in the design and is available from the CML pin.
Optimum performance is achieved when the common-mode
voltage of the analog input is set by the CML pin voltage (typically
0.55 × AVDD). The CML pin must be decoupled to ground by a
0.1 μF capacitor as described in the Applications Information
section.
Differential Input Configurations
Optimum performance is achieved while driving the AD9600
in a differential input configuration. For baseband applications,
the AD8138, ADA4937-2, and
provide excellent performance and a flexible interface to the
VIN+
VIN–
C
C
PIN, PAR
PIN, PAR
Figure 45. Switched-Capacitor SHA Input
S
S
H
Converters” (Volume 39, April 2005)
ADA4938-2
C
C
S
S
“Transformer-Coupled
CM
= 0.55 × AVDD is
differential drivers
C
C
S
S
H
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AD9600