AD9601 Analog Devices, AD9601 Datasheet - Page 23

• Manufacturer Part Number: AD9601
• Description: 10-Bit, 200 MSPS/250 MSPS 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9601

• Resolution (bits): 10bit
• # Chan: 1
• Sample Rate: 250MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 1 V p-p,1.25 V p-p,1.5 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

MEMORY MAP
READING THE MEMORY MAP TABLE
Each row in the memory map table has eight address locations.
The memory map is roughly divided into three sections: chip
configuration register map (Address 0x00 to Address 0x02),
transfer register map (Address 0xFF), and program register map
(Address 0x08 to Address 0x2A).
The Addr (Hex) column of the memory map indicates the
register address in hexadecimal, and the Default Value (Hex)
column shows the default hexadecimal value that is already
written into the register. The Bit 7 (MSB) column is the start of
the default hexadecimal value given. For example, Hexadecimal
Address 0x09, clock, has a hexadecimal default value of 0x01.
This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0,
Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. The
default value enables the duty cycle stabilizer. Overwriting this
default so that Bit 0 = 0 disables the duty cycle stabilizer. For more
information on this and other functions, consult the Interfacing
to High Speed ADCs via SPI user manual at www.analog.com.
Table 12. Memory Map Register
Addr
(Hex)
Chip Configuration Registers
00
01
02
Transfer Register
FF
ADC Functions
08
Parameter Name
chip_port_config
chip_id
chip_grade
device_update
modes
Bit 7
(MSB)
0
0
0
0
Bit 6
LSB
first
0
0
0
Bit 5
Soft reset
0
0
PDWN:
0 = full
(default)
1 =
standby
8-bit chip ID, Bits[7:0]
Bit 4
1
0
0
Rev. 0 | Page 23 of 32
01 = 200 MSPS
10 = 250 MSPS
AD9601 = 0x36
Speed grade:
Bit 3
1
0
0
RESERVED LOCATIONS
Undefined memory locations should not be written to other
than their default values suggested in this data sheet. Addresses
that have values marked as 0 should be considered reserved and
have a 0 written into their registers during power-up.
DEFAULT VALUES
Coming out of reset, critical registers are preloaded with default
values. These values are indicated in Table 12. Other registers
do not have default values and retain the previous value when
exiting reset.
LOGIC LEVELS
An explanation of various registers follows: “Bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit. ” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit. ”
Bit 2
Soft reset
X
0
Note: external PDWN pin overrides
000 = normal (power-up, default)
Internal power-down mode:
011 = normal (power-up)
001 = full power-down
010 = standby
this setting
Bit 1
LSB first
X
0
Bit 0
(LSB)
0
X
SW
transfer
Default
Value
(Hex)
0x18
Read-
only
Read-
only
0x00
0x00
Default Notes/
Comments
The nibbles
should be
mirrored by the
user so that LSB
or MSB first mode
registers correctly,
regardless of shift
mode.
Default is unique
chip ID, different
for each device.
This is a read-
only register.
Child ID used to
differentiate
graded devices.
Synchronously
transfers data
from the master
shift register to
the slave.
Determines
various generic
modes of chip
operation.
AD9601