AD9627-11 Analog Devices, AD9627-11 Datasheet
AD9627-11
Specifications of AD9627-11
Related parts for AD9627-11
AD9627-11 Summary of contents
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... Pin compatibility with the AD9640, AD9627, and AD9600 for a simple migration from 11 bits to 14 bits, 12 bits bits. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved. AD9627-11 SDIO/ SCLK/ DCS DFS CSB DRVDD ...
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... Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Specifications ..................................................................................... 5 ADC DC Specifications—AD9627-11-105/AD9627-11-150 . 5 ADC AC Specifications—AD9627-11-105/AD9627-11-150 . 6 Digital Specifications ................................................................... 7 Switching Specifications—AD9627-11-105/AD9627-11-150 9 Timing Specifications ................................................................ 10 Absolute Maximum Ratings .......................................................... 12 Thermal Characteristics ............................................................ 12 ESD Caution ................................................................................ 12 Pin Configurations and Function Descriptions ......................... 13 Equivalent Circuits ...
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... REVISION HISTORY 5/10—Rev Rev. B Deleted CP-64-3 Package .................................................. Universal Added CP-64-6 Package .................................................... Universal Changed AD9627BCPZ11-150 to AD9627-11-150 and AD9627BCPZ11-105 to AD9627-11-105 Throughout ................ 5 Changes to Figure 6 ......................................................................... 13 Changes to Figure 7 ......................................................................... 15 Updated Outline Dimensions ........................................................ 71 Changes to Ordering Guide ........................................................... 71 9/09—Rev Rev. A Changes to Table 4 ............................................................................ 9 Changes to Figure 3 ......................................................................... 11 Changes to Figure 11, Figure 12, and Figure 14 ...
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... CMOS or 1.8 V LVDS. Flexible power-down options allow significant power savings, when desired. Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface. The AD9627-11 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. Rev Page ...
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... SPECIFICATIONS ADC DC SPECIFICATIONS—AD9627-11-105/AD9627-11-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted. Table 1. Parameter Temperature RESOLUTION Full ACCURACY No Missing Codes ...
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... AD9627-11 ADC AC SPECIFICATIONS—AD9627-11-105/AD9627-11-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted. Table 2. 1 Parameter SIGNAL-TO-NOISE RATIO (SNR 2.3 MHz ...
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... Full Full Full Full Full Full Full Full Full Full Full Full Full 1 Full Full Full Full Full Full 2 Full Full Full Full Rev Page AD9627-11 Min Typ Max CMOS/LVDS/LVPECL 1.2 0.2 6 GND − 0.3 AVDD + 1.6 1.1 AVDD 1.2 3.6 0 0.8 −10 +10 −10 + CMOS 1.2 GND − 0.3 AVDD + 1 ...
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... AD9627-11 Parameter Input Resistance Input Capacitance DIGITAL OUTPUTS CMOS Mode—DRVDD = 3.3 V High Level Output Voltage μ 0 Low Level Output Voltage μA OL CMOS Mode—DRVDD = 1.8 V High Level Output Voltage μ 0 Low Level Output Voltage ...
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... SWITCHING SPECIFICATIONS—AD9627-11-105/AD9627-11-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 4. Parameter CLOCK INPUT PARAMETERS Input Clock Rate Conversion Rate 1 DCS Enabled 1 DCS Disabled CLK Period—Divide-by-1 Mode (t ...
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... AD9627-11 TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments SYNC TIMING REQUIREMENTS t SYNC to rising edge of CLK setup time SSYNC t SYNC to rising edge of CLK hold time HSYNC SPI TIMING REQUIREMENTS t Setup time between the data and the rising edge of SCLK DS t Hold time between the data and the rising edge of SCLK ...
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... N – – – DCO t t SSYNC HSYNC Figure 4. SYNC Input Timing Requirements t SSCLKSDO DATA Figure 5. Signal Monitor SPORT Output Timing (Divide-by-2 Mode) Rev Page AD9627- – – – – ...
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... AD9627-11 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter ELECTRICAL AVDD, DVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD VIN+A/VIN+B, VIN−A/VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VREF to AGND SENSE to AGND CML to AGND RBIAS to AGND CSB to AGND SCLK/DFS to DRGND ...
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... Channel A Fast Detect Indicator. See Table 14 for details. Channel B Fast Detect Indicator. See Table 14 for details. Channel B Fast Detect Indicator. See Table 14 for details. Channel B Fast Detect Indicator. See Table 14 for details. Channel B Fast Detect Indicator. See Table 14 for details. Rev Page AD9627-11 48 SCLK/DFS 47 SDIO/DCS 46 ...
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... AD9627-11 Pin No. Mnemonic Type Digital Input 52 SYNC Input Digital Outputs 15 D0A (LSB) Output 16 D1A Output 17 D2A Output 18 D3A Output 19 D4A Output 22 D5A Output 23 D6A Output 25 D7A Output 26 D8A Output 27 D9A Output 28 D10A (MSB) Output 61 D0B (LSB) Output 62 D1B Output 63 D2B Output ...
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... Channel A/Channel B LVDS Fast Detect Indicator 2—Complement. See Table 14 for details. Channel A/Channel B LVDS Fast Detect Indicator 3—True. See Table 14 for details. Channel A/Channel B LVDS Fast Detect Indicator 3—Complement. See Table 14 for details. Digital Synchronization Pin. Slave mode only. Rev Page AD9627-11 48 SCLK/DFS 47 SDIO/DCS ...
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... AD9627-11 Pin No. Mnemonic Type Digital Outputs 7 D0+ (LSB) Output 6 D0− (LSB) Output 9 D1+ Output 8 D1− Output 13 D2+ Output 12 D2− Output 15 D3+ Output 14 D3− Output 17 D4+ Output 16 D4− Output 19 D5+ Output 18 D5− Output 23 D6+ Output 22 D6− ...
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... Figure 10. Digital Output DRVDD DVDD 26kΩ 1kΩ SDIO/DCS Figure 11. Equivalent SDIO/DCS or SMI SDFS Circuit CLK– DVDD DRVDD Rev Page AD9627-11 DVDD 1kΩ SCLK/DFS 26kΩ Figure 12. Equivalent SCLK/DFS Input Circuit 1kΩ SENSE Figure 13. Equivalent SENSE Circuit DVDD DVDD 26kΩ ...
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... SFDR = 79.0dBc –40 –60 THIRD SECOND –80 HARMONIC HARMONIC –100 –120 FREQUENCY (MHz) Figure 20. AD9627-11-150 Single-Tone FFT with f 0 150MSPS 337MHz @ –1dBFS SNR = 64.6dB (65.4dBFS) –20 ENOB = 10.6 BITS SFDR = 76.0dBc –40 –60 THIRD HARMONIC –80 –100 –120 0 10 ...
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... MHz Figure 25. AD9627-11-105 Single-Tone FFT with –20 –40 –60 –80 –100 –120 2.3 MHz Figure 26. AD9627-11-105 Single-Tone FFT with –20 –40 –60 –80 –100 –120 30.3 MHz Figure 27. AD9627-11-105 Single-Tone FFT with f IN Rev Page ...
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... IN SFDR = +25°C 300 350 400 450 Figure 33. AD9627-11-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (A Rev Page SFDR = +85° SFDR = +25°C 80 SFDR = –40° SNR = +25°C 60 SNR = +85°C SNR = –40°C ...
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... SFDR (dBc) –40 IMD3 (dBc) –60 SFDR (dBFS) –80 –100 IMD3 (dBFS) –120 –90 –78 –66 –54 –42 INPUT AMPLITUDE (dBFS) Figure 34. AD9627-11-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (A with f = 169.1 MHz 172.1 MHz, f IN1 IN2 0 –20 –40 –60 –80 –100 –120 0 15.36 30 ...
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... MHz IN Rev Page 100 95 SFDR DCS SFDR DCS OFF 75 SNR DCS SNR DCS OFF DUTY CYCLE (%) Figure 43. AD9627-11 SNR/SFDR vs. Duty Cycle with f 95 SFDR SNR 65 60 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 INPUT COMMON-MODE VOLTAGE (V) Figure 44. AD9627-11 SNR/SFDR vs. Input Common Mode (VCM) ...
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... THEORY OF OPERATION The AD9627-11 dual ADC design can be used for diversity recep- tion of signals, where the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent analog inputs. The user can sample ...
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... AD9627-11 The output common-mode voltage of the AD8138 is easily set with the CML pin of the AD9627-11 (see Figure 46), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. 499Ω p-p 49.9Ω 499Ω AD8138 C 0.1µF 523Ω ...
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... The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference. 1.0µF If the internal reference of the AD9627-11 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 53 shows how the internal reference voltage is affected by loading ...
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... Jitter Considerations section. Figure 56 and Figure 57 show two preferred methods for clocking the AD9627-11 (at clock rates up to 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF balun transformer. ...
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... RESISTOR IS OPTIONAL. Figure 61. Single-Ended 3.3 V CMOS Sample Clock (Up to 150 MSPS) Input Clock Divider The AD9627-11 contains an input clock divider with the ability to divide the input clock by integer values between 1 and divide ratio other than 1 is selected, the duty cycle stabilizer is automatically enabled ...
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... DIGITAL OUTPUTS 0.4 The AD9627-11 output drivers can be configured to interface with 1 3.3 V CMOS logic families by matching DRVDD to the digital supply of the interfaced logic. The AD9627-11 can 0.3 also be configured for LVDS outputs using a DRVDD supply voltage of 1.8 V. 0.2 In CMOS output mode, the output drivers are sized to provide sufficient output current to drive a wide variety of logic families ...
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... DCS disabled These transients can degrade converter dynamic performance. DCS enabled (default) The lowest typical conversion rate of the AD9627- MSPS. At clock rates below 10 MSPS, dynamic performance can degrade. Data Clock Output (DCO) The AD9627-11 provides two data clock output (DCO) signals intended for capturing the data in an external register ...
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... FAST DETECT OVERVIEW The AD9627-11 contains circuitry to facilitate fast overrange detec- tion, allowing very flexible external gain control implementations. Each ADC has four fast detect (FD) output pins that are used to output information about the current state of the ADC input level ...
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... ADC clock cycles. An overrange at the input is indicated by this bit 12 clock cycles after it occurs. GAIN SWITCHING The AD9627-11 includes circuitry that is useful in applications either where large dynamic ranges exist or where gain ranging converters are employed. This circuitry allows digital thresholds to be set such that an upper threshold and a lower threshold can be programmed ...
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... AD9627-11 Increment Gain (IG) and Decrement Gain (DG) The increment gain and decrement gain indicators are intended to be used together to provide information to enable external gain control. The decrement gain indicator works in conjunction with the coarse upper threshold bits, asserting when the input magnitude is greater than the 3-bit value in the coarse upper threshold register (Address 0x105) ...
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... SPORT serial port. The monitor period timer is reloaded with the value in the SMPR, and the countdown is restarted. In addition, the first input sample signal power is updated in the accumulator, and the accumulation continues with the subsequent input samples. Rev Page AD9627-11 DOWN IS COUNT = 1? COUNTER LOAD TO ...
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... AD9627-11 Figure 67 illustrates the rms magnitude monitoring logic. FROM MEMORY MAP SIGNAL MONITOR DOWN IS COUNT = 1? PERIOD REGISTER COUNTER LOAD FROM CLEAR LOAD INPUT SIGNAL MONITOR PORTS ACCUMULATOR REGISTER (SMR) Figure 67. ADC Input RMS Magnitude Monitoring Block Diagram For rms magnitude mode, the value in the signal monitoring result (SMR) register is a 20-bit fixed-point number ...
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... Register 0x10C, Bits[5:2] (values between 0 and 13 are valid for k; programming provides the same result as programming 13 the AD9627-11 ADC sample rate in hertz (Hz). CLK DC Correction Readback The current dc correction value can be read back in Register 0x10D and Register 0x10E for Channel A and Register 0x10F and Register 0x110 for Channel B ...
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... The AD9627-11 includes built-in test features designed to enable verification of the integrity of each channel as well as facilitate board level debugging. A BIST (built-in self-test) feature is included that verifies the integrity of the digital datapath of the AD9627-11. Various output test options are also provided to place predictable values on the outputs of the AD9627-11. ...
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... CHANNEL/CHIP SYNCHRONIZATION The AD9627-11 has a SYNC input that offers the user flexible synchronization options for synchronizing the internal blocks. The clock divider sync feature is useful for guaranteeing synchro- nized sample clocks across multiple ADCs. The signal monitor block can also be synchronized using the SYNC input, allowing properties of the input signal to be measured during a specific time period ...
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... If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9627-11 to prevent these signals from transi- tioning at the converter inputs during critical sampling periods. Some pins serve a dual function when the SPI interface is not being used ...
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... Table 21 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in Application Note AN-877, Interfacing to High Speed ADCs via SPI. The AD9627-11 part-specific features are described in detail following Table 22, the external memory map register table. Table 21. Features Accessible Using the SPI ...
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... Address 0x18). If the entire address location is open (for example, Address 0x13), this address location should not be written. Default Values After the AD9627-11 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 22. Logic Levels An explanation of logic level terminology follows: ...
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... Open Open (Global) 0x0D Test Mode Open Open (Local) Bit 5 Bit 4 Bit 3 Bit 2 Soft reset 1 1 Soft reset 8-bit Chip ID[7:0] (AD9627-11 = 0x20) (default) Speed grade ID Open Open 00 = 150 MSPS 10 = 105 MSPS Open Open Open Open Open Open Open Open External Open ...
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... AD9627-11 Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x0E BIST Enable Open Open (Local) 0x10 Offset Adjust Open Open (Local) 0x14 Output Mode Drive Output strength type 3 CMOS CMOS LVDS ANSI (global) LVDS 1.8 V CMOS or reduced LVDS ...
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... Signal Monitor Period[7:0] Signal Monitor Period[15:8] Signal Monitor Period[23:16] Signal Monitor Result Channel A[7:0] Rev Page AD9627-11 Default Default Bit 0 Value Notes/ Bit 1 (LSB) (Hex) Comments 0x00 0x00 In ADC clock ...
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... AD9627-11 Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x117 Signal Monitor Result Channel A Register 1 (Global) 0x118 Signal Monitor Open Open Result Channel A Register 2 (Global) 0x119 Signal Monitor Result Channel B Register 0 (Global) 0x11A Signal Monitor Result Channel B Register 1 (Global) 0x11B Signal Monitor ...
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... Register 0x10C, Bits[5:2] (values between 0 and 13 are valid for k; programming provides the same result as programming 13 the AD9627-11 ADC sample rate in hertz (Hz). CLK Bit 1—DC Correction for Signal Path Enable Setting Bit 1 high causes the output of the dc measurement block to be summed with the data in the signal path to remove the dc offset from the signal path ...
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... AD9627-11 Signal Monitor Period (Register 0x113 to Register 0x115) Register 0x113, Bits[7:0]—Signal Monitor Period[7:0] Register 0x114, Bits[7:0]—Signal Monitor Period[15:8] Register 0x115, Bits[7:0]—Signal Monitor Period[23:16] This 24-bit value sets the number of clock cycles over which the signal monitor performs its operation. Although this register defaults to 64 (0x40), the minimum value for this register is 128 (0x80) cycles ...
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... The CML pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 47. RBIAS The AD9627-11 requires that a 10 kΩ resistor be placed between the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance. ...
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... AD9627-11 EVALUATION BOARD The AD9627-11 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially through a double balun configuration (default) or optionally through the AD8352 differential driver. The ADC can also be driven in a single-ended fashion ...
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... SDIO pin to the on-board SPI circuitry (see the Serial Port Interface (SPI) section). ALTERNATIVE CLOCK CONFIGURATIONS Two alternate clocking options are provided on the AD9627-11 evaluation board. The first option is to use an on-board crystal oscillator (Y1) to provide the clock input to the part. To enable this crystal, Resistor R8 (0 Ω ...
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... AD9627-11 ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION This section provides a brief description of the alternative analog input drive configuration using the AD8352. When using this particular drive option, some additional components need to be populated. For more details on the AD8352 differential driver, including how it works and its optional pin settings, consult the AD8352 data sheet ...
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... SCHEMATICS M OH 10K R41 100 R127 4.12K R126 DNP R36 24 24.9 R29 R35 F Figure 73. Evaluation Board Schematic, Channel A Analog Inputs Rev Page AD9627-11 07054-073 M OH 57.6 R5 OHM 33 OHM 33 R43 R47 OHM 57 57.6 R1 R28 2 2 ...
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... AD9627- 10K R53 D AMPVD M OH 100 R129 4.12K R128 DNP R68 M OH 24.9 OHM 24.9 R134 R135 F Figure 74. Evaluation Board Schematic, Channel B Analog Inputs Rev Page 07054-074 M OH 57.6 R72 OHM 33 OHM 33 R70 R71 OHM 0 F R69 F OHM 57.6 OHM 57.6 R52 R51 2 2 ...
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... M OH 10K M OH 10K R85 R82 Figure 75. Evaluation Board Schematic, DUT Clock Input TP2 R83 DNP R34 57 57.6 R30 Rev Page AD9627-11 07054-075 ...
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... AD9627- VS_OUT67_ 50 2 VS_OUT67_ 51 V VS_OUT01_DI 52 OUT1B 53 OUT1 54 VS_OUT01_DRV 55 OUT0B 56 OUT0 57 VS_REF 4.12K 58 RSET_CLOCK R12 59 GND_REF 60 VS_PRESCALER 61 2 VS_PLL_ 5.1K 62 CP_RSET R11 63 REFINB 64 REFIN OHM 100 R75 OHM 100 R9 Figure 76. Evaluation Board Schematic, Optional AD9516 Clock Circuit Rev Page ...
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... R100 M OH 24.9 R87 TP1 RES060 M OH 57.6 R45 2 Figure 77. Evaluation Board Schematic, Optional AD9516 Loop Filter/VCO and SYNC Input Rev Page RES040 2 RES040 M OH 10K M OH 10K R107 R109 2 RES040 2 RES040 M OH 10K M OH 10K R106 R108 AD9627-11 07054-077 ...
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... AD9627-11 DVDD 8 RPAK FD0A 1 16 FD1A 2 15 FD2A 3 14 FD3A PWR_SD PWR_SCL PWR_SDFS 8 9 RES040 R112 17 D2A 18 D3A 19 D4A 20 DRGND1 21 DRVDD1 22 D5A 23 D6A 24 DVDD1 25 D7A 26 D8A 27 D9A 28 D10A_MSB_ 29 FD0A 30 FD1A 31 FD2A 32 FD3A Figure 78. Evaluation Board Schematic, DUT Rev ...
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... RES040 M OH 10K R118 VAL R130 2 RES040 M OH 10K R140 Figure 79. Evaluation Board Schematic, Digital Output Interface Rev Page AD9627-11 07054-079 M OH 100 R77 ...
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... AD9627-11 Figure 80. Evaluation Board Schematic, SPI Circuitry Rev Page 07054-080 2 RES040 OHM 10K R65 ...
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... M KOH 140 R13 GND 4 1 RES0603 M OH 261 A C R16 CR7 SJ35 2 1 S2A_REC T Figure 81. Evaluation Board Schematic, Power Supply Rev Page 07054-081 M KOH 78.7 R14 1 TP25 AD9627-11 ...
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... AD9627- SJ36 SJ37 M KOH 140 Figure 82. Evaluation Board Schematic, Power Supply (Continued) Rev Page 07054-082 M KOH 78 ...
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... EVALUATION BOARD LAYOUTS Figure 83. Evaluation Board Layout, Primary Side Rev Page AD9627-11 ...
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... AD9627-11 Figure 84. Evaluation Board Layout, Ground Plane Rev Page ...
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... Figure 85. Evaluation Board Layout, Power Plane Rev Page AD9627-11 ...
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... AD9627-11 Figure 86. Evaluation Board Layout, Power Plane Rev Page ...
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... Figure 87. Evaluation Board Layout, Ground Plane Rev Page AD9627-11 ...
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... AD9627-11 Figure 88. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev Page ...
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... Figure 89. Evaluation Board Layout, Silkscreen, Primary Side Rev Page AD9627-11 ...
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... AD9627-11 Figure 90. Evaluation Board Layout, Silkscreen, Secondary Side Rev Page ...
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... R0603 NIC Components R0402SM NIC Components R0603 NIC Components R0603 NIC Components R0603 NIC Components R0603 NIC Components R0402SM NIC Components Rev Page AD9627-11 Mfg. Part Number GRM155R71C104KA88D GJM1555C1H180JB01J GJM1555C1H4R7CB01J GRM155R71H102KA01D GR4M219R61A105KC01D GRM31CR61C106KC31L HSMS-2822-BLKG LNJ208R8ARA S2A-TP SK33-TP BNX016-01 NANOSMDC150F-2 TWS-1003-08-G-S ...
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... W, 1% resistor 34 4 S2, S3, S5, S12 SMA, inline, male, coaxial connector 35 1 SJ35 0 Ω, 1 resistor Balun IC, AD9627- Clock distribution, PLL Dual inverter Dual buffer IC, open-drain circuits UHS dual buffer IC ...
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... Body, Very Thin Quad (CP-64-6) Dimensions shown in millimeters Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Evaluation Board Rev Page AD9627-11 PIN 1 INDICATOR 64 1 7.55 EXPOSED PAD (BOTTOM VIEW) 7. ...
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... AD9627-11 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07054-0-5/10(B) Rev Page ...