AD9230 Analog Devices, AD9230 Datasheet
AD9230
Specifications of AD9230
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AD9230 Summary of contents
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... LVDS (ANSI-644) compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing. Fabricated on an advanced CMOS process, the AD9230 is available in a 56-lead LFCSP, specified over the industrial temperature range (−40°C to +85°C). ...
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... Theory of Operation ...................................................................... 21 Analog Input and Voltage Reference ....................................... 21 Clock Input Considerations...................................................... 22 Power Dissipation and Power-Down Mode ........................... 23 Digital Outputs ........................................................................... 23 Timing ......................................................................................... 24 RBIAS........................................................................................... 24 AD9230 Configuration Using the SPI ..................................... 24 Hardware Interface..................................................................... 25 Configuration Without the SPI ................................................ 25 Memory Map .................................................................................. 27 Reading the Memory Map Table.............................................. 27 Reserved Locations .................................................................... 27 Default Values ............................................................................. 27 Logic Levels ...
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... MHz sine input at rated sample rate. AVDD DRVDD 4 Single data rate mode; this is the default mode of the AD9230. 5 Double data rate mode; user-programmable feature. See the Memory Map section. = +85° −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted. ...
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... Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed. 3 140 MHz for the AD9230-170 speed grade, 170 MHz for the AD9230-210 and AD9230-250 speed grades. = +85° −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted. ...
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... AVDD 3.6 1.2 3.6 0.8 0 0.8 +10 −10 +10 +10 −10 + 0.8 × VDD 0.2 × 0.2 × AVDD AVDD 0 0 −60 − 454 247 454 1.375 1.125 1.375 AD9230 Unit μA μA kΩ μA μA μA μ ...
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... See Figure 2. 2 See Figure 3. = +85° −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted. MAX IN AD9230-170 AD9230-210 Min Typ Max Min 170 210 40 2.65 2.9 2.15 2.65 2.9 2.15 3.0 0.2 0.2 3.9 −0.3 0.1 0.5 −0.3 7 3.8 0.2 0.2 3.9 −0.5 0.1 0.3 −0.5 7 0.2 Rev Page AD9230-250 Typ Max 250 40 2.4 1.8 2.0 2.4 1.8 2.0 3.0 3.0 0.2 0.2 0.2 0.2 3.9 3.9 0.1 0.5 −0.3 0 3.8 3.8 0.2 0.2 0.2 0.2 3.9 3.9 0.1 0.3 −0.5 0 0.2 Unit MSPS ...
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... Rev Page – – – – – – – – 4 D11 D5 D11 D5 D11 N – – – – – 4 AD9230 – – 3 ...
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... AD9230 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter ELECTRICAL AVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD D0+/D0− through D13+/D13− to DRGND DCO to DRGND OR to DGND CLK+ to AGND CLK− to AGND VIN+ to AGND VIN− to AGND SDIO/DCS to DGND PDWN to AGND CSB to AGND ...
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... D1 True Output Bit. D2 Complement Output Bit. D2 True Output Bit. D3 Complement Output Bit. D3 True Output Bit. D4 Complement Output Bit. D4 True Output Bit. Rev Page AVDD 41 AVDD 40 CML 39 AVDD 38 AVDD 37 AVDD 36 VIN– 35 VIN+ 34 AVDD 33 AVDD 32 AVDD 31 RBIAS 30 AVDD 29 PWDN AD9230 ...
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... AD9230 Pin No. Mnemonic 5 D5− 6 D5+ 9 D6− 10 D6+ 11 D7− 12 D7+ 13 D8− 14 D8+ 15 D9− 16 D9+ 17 D10− 18 D10+ 19 D11− 20 D11+ 21 OR− 22 OR+ 1 AGND and DRGND should be tied to a common quiet ground plane. Description D5 Complement Output Bit. ...
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... D2/D8 Complement Output Bit. D2/D8 True Output Bit. D3/D9 Complement Output Bit. D3/D9 True Output Bit. D4/D10 Complement Output Bit. D4/D10 True Output Bit. D5/D11 Complement Output Bit (MSB). D5/D11 True Output Bit (MSB). Rev Page AD9230 42 AVDD 41 AVDD 40 CML 39 AVDD 38 AVDD 37 AVDD 36 VIN– 35 VIN+ ...
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... AD9230 Pin No. Mnemonic 9 OR− DNC 21 DNC/(OR−) 22 DNC/(OR+) 1 AGND and DRGND should be tied to a common quiet ground plane. Description D6 Complement Output Bit. (This pin is disabled if Pin 21 is reconfigured through the SPI to be OR−.) D6 True Output Bit. (This pin is disabled if Pin 22 is reconfigured through the SPI to be OR+.) Do Not Connect ...
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... AVDD V CML ~1.4V = ~1.4 V) Rev Page AVDD 26kΩ 1kΩ CSB Figure 9. Equivalent CSB Input Circuit DRVDD V+ V– DATAOUT– DATAOUT+ V– V+ Figure 10. LVDS Outputs (Dx+, Dx−, OR+, OR−, DCO+, DCO−) DRVDD 1kΩ SDIO/DCS Figure 11. Equivalent SDIO/DCS Input Circuit AD9230 ...
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... ENOB: 10.5 BITS SFDR: 78dBc –40 –60 –80 –100 –120 –140 FREQUENCY (MHz) Figure 13. AD9230-170 64k Point Single-Tone FFT; 170 MSPS, 70.3 MHz 0 –20 –40 –60 –80 –100 –120 –140 FREQUENCY (MHz) Figure 14. AD9230-170 64k Point Single-Tone FFT; 170 MSPS, 140.3 MHz = 25° ...
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... Figure 22. AD9230-170 Two-Tone SFDR vs. Input Amplitude; 170 MSPS, 380 370 360 350 340 330 320 310 300 160 180 Rev Page AD9230 1023 2047 3071 OUTPUT CODE Figure 21. AD9230-170 DNL ...
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... Figure 27. AD9230-210 Single-Tone SNR/SFDR vs. Input Frequency (f 210MSPS 170.3MHz @ –1.0dBFS SNR: 631.7dB ENOB: 9.9 BITS SFDR: 67dBc 80 100 Figure 28. AD9230-210 SNR/SFDR vs. Input Amplitude; 210 MSPS, 170.3 MHz Rev Page 40000 INPUT REFERRED NOISE: 0.70 LSBs 35000 30000 25000 20000 15000 10000 ...
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... Figure 33. AD9230-210 Two-Tone SFDR vs. Input Amplitude; 210 MSPS, 400 390 380 370 360 350 340 330 320 240 Rev Page AD9230 1023 2047 3071 OUTPUT CODE Figure 32. AD9230-210 DNL ...
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... SNR: 63.9dB ENOB: 10.5 BITS SFDR: 79dBc 80 100 120 Figure 38. AD9230-250 Single-Tone SNR/SFDR vs. Input Frequency (f 80 100 120 Figure 39. AD9230-250 SNR/SFDR vs. Input Amplitude; 250 MSPS, 170.3 MHz Rev Page 40000 INPUT REFERRED NOISE: 0.71 LSBs 35000 30000 25000 20000 15000 10000 5000 0 N – ...
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... Figure 45. AD9230-250 64k Point FFT; Four W-CDMA Carriers 184 MHz, Rev Page AD9230 1023 2047 3071 OUTPUT CODE Figure 43. AD9230-250 DNL; 250 MSPS IMD3 (dBFS) SFDR (dBFS) SFDR (dBc) –80 – ...
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... INPUT CLOCK DUTY CYCLE (% CLK+ HIGH) Figure 49. SNR/SFDR vs. Sample Clock Duty Cycle; 250 MSPS, 170.3 MHz @ −1 dBFS AD9230-250 AD9230-210 AD9230-170 –40 – TEMPERATURE (°C) Figure 50. Gain vs. Temperature AD9230-250 AD9230-210 AD9230-170 TEMPERATURE (°C) Figure 51. Offset vs. Temperature 90 100 100 120 70 ...
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... During power-down, the output buffers go into a high impedance state. ANALOG INPUT AND VOLTAGE REFERENCE The analog input to the AD9230 is a differential buffer. For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched such that common-mode settling errors are symmetrical ...
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... This allows a wide range of clock input duty cycles without affecting the performance of the AD9230. When the DCS is on, noise and distortion perfor- mance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, 0.1µ ...
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... ANALOG INPUT FREQUENCY (MHz) Figure 60. Ideal SNR vs. Input Frequency and Jitter POWER DISSIPATION AND POWER-DOWN MODE As shown in Figure 42, the power dissipated by the AD9230 is proportional to its sample rate. The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. ...
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... AD9230 and must be captured on the rising edge of the DCO. In double data rate mode (DDR), data is clocked out of the AD9230 and must be captured on the rising and falling edges of the DCO See the timing diagrams shown in Figure 2 and Figure 3 for more information ...
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... The pins described in Table 9 comprise the physical interface between the user’s programming device and the serial port of the AD9230. All serial pins are inputs, which is an open-drain output and should be tied to an external pull-up or pull-down resistor (suggested value of 10 kΩ). ...
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... AD9230 Table 11. Serial Timing Definitions Parameter Timing (minimum, ns CLK EN_SDIO t 5 DIS_SDIO Table 12. Output Data Format Input (V) Condition (V) VIN+ − VIN− < 0.62 VIN+ − VIN− = 0.62 VIN+ − VIN− ...
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... Similarly, “clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit. ” Bit 5 Bit 4 Bit 3 Bit 2 Soft 1 1 Soft reset reset 8-bit chip ID, Bits[7:0] AD9230 = 0x0C 0 Speed grade 250 MSPS 01 = 210 MSPS 10 = 170 MSPS Rev Page AD9230 ...
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... AD9230 Addr. Bit 7 (Hex) Parameter Name (MSB) Bit 6 ADC Functions 08 modes clock test_io OF ain_config output_mode 0 15 output_adjust output_phase Output 0 clock polarity 1 = inverted 0 = normal (default) Bit 5 Bit 4 Bit 3 Bit 2 PDWN Internal power-down mode full 000 = normal (power-up, ...
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... Input voltage range setting: 10000 = 0.98 V 10001 =1.00 V 10010 = 1.02 V 10011 =1.04 V … 11111 = 1.23 V 00000 = 1.25 V 00001 = 1.27 V … 01110 = 1.48 V 01111 = 1.50 V Rev Page AD9230 Def. Bit 0 Value Default Notes/ Bit 1 (LSB) (Hex) Comments 00000001 position enable: (DDR mode ...
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... Package Description 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] LVDS Evaluation Board with AD9230BCPZ-170 LVDS Evaluation Board with AD9230BCPZ-210 LVDS Evaluation Board with AD9230BCPZ-250 Rev Page ...
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... NOTES Rev Page AD9230 ...
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... AD9230 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06002-0-2/07(0) Rev Page ...