AD9230 Analog Devices, AD9230 Datasheet - Page 26

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AD9230

Manufacturer Part Number
AD9230
Description
12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter
Manufacturer
Analog Devices
Datasheet

Specifications of AD9230

Resolution (bits)
12bit
# Chan
1
Sample Rate
250MSPS
Interface
LVDS,Par
Analog Input Type
Diff-Uni
Ain Range
1.25 V p-p
Adc Architecture
Pipelined
Pkg Type
CSP

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AD9230
Table 11. Serial Timing Definitions
Parameter
t
t
t
t
t
t
t
t
t
Table 12. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
DS
DH
CLK
S
H
HI
LO
EN_SDIO
DIS_SDIO
Condition (V)
< 0.62
= 0.62
= 0
= 0.62
> 0.62 + 0.5 LSB
Timing (minimum, ns)
5
2
40
5
2
16
16
1
5
Description
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 64)
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 64)
Offset Binary
Output Mode
D11 to D0
0000 0000 0000
0000 0000 0000
0000 0000 0000
1111 1111 1111
1111 1111 1111
Rev. 0 | Page 26 of 32
Twos Complement Mode
D11 to D0
0000 0000 0000
0000 0000 0000
0000 0000 0000
1111 1111 1111
1111 1111 1111
Gray Code Mode
(SPI Accessible)
D11 to D0
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
OR
1
0
0
0
1

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