AD7652 Analog Devices, AD7652 Datasheet - Page 20

• Manufacturer Part Number: AD7652
• Manufacturer: Analog Devices

Specifications of AD7652

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 500kSPS
• Interface: Par,Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: Uni (Vref),Uni 2.5V
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7652
DIGITAL INTERFACE
The AD7652 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or a parallel
interface. The serial interface is multiplexed on the parallel data
bus. The AD7652 digital interface also accommodates both 3 V
and 5 V logic by simply connecting the OVDD supply pin of the
AD7652 to the host system interface digital supply. Finally, by
using the OB/ 2C input pin, both twos complement or straight
binary coding can be used.
The two signals, CS and RD , control the interface. CS and RD
have a similar effect because they are OR’d together internally.
When at least one of these signals is HIGH, the interface
outputs are in high impedance. Usually CS allows the selection
of each AD7652 in multicircuit applications and is held LOW in
a single AD7652 design. RD is generally used to enable the
conversion result on the data bus.
PARALLEL INTERFACE
The AD7652 is configured to use the parallel interface when
SER/ PAR is held LOW. The data can be read either after each
conversion, which is during the next acquisition phase, or
during the following conversion, as shown in F
Figure 30
conversion, however, it is recommended that it is read only
during the first half of the conversion phase. This avoids any
potential feedthrough between voltage transients on the digital
interface and the most critical analog conversion circuitry.
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in
MSB is output on D[15:8] when BYTESWAP is LOW. When
BYTESWAP is HIGH, the LSB and MSB bytes are swapped and
the LSB is output on D[15:8] and the MSB is output on D[7:0].
By connecting BYTESWAP to an address line, the 16-bit data
can be read in two bytes on either D[15:8] or D[7:0].
SERIAL INTERFACE
The AD7652 is configured to use the serial interface when
SER/ PAR is held HIGH. The AD7652 outputs 16 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin. The output data
is valid on both the rising and falling edges of the data clock.
, respectively. When the data is read during the
Figure 31
, the LSB byte is output on D[7:0] and the
igure 29
and
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BUSY
CNVST,
DATA
CS = 0
PINS D[15:8]
BUS
BUSY
BYTESWAP
DATA
PINS D[7:0]
RD
Figure 30. Slave Parallel Data Timing for Reading (Read during Convert)
CS
BUS
Figure 29. Slave Parallel Data Timing for Reading (Read after Convert)
RD
RD
CS
HI-Z
HI-Z
t
t
12
12
t
3
Figure 31. 8-Bit Parallel Interface
CONVERSION
CONVERSION
PREVIOUS
CURRENT
t
t
12
1
HIGH BYTE
LOW BYTE
t
t
13
13
t
4
t
12
HIGH BYTE
LOW BYTE
02965-0-025
02964-0-013
02964-0-014
HI-Z
HI-Z
t
13