AD7652 Analog Devices, AD7652 Datasheet - Page 21

• Manufacturer Part Number: AD7652
• Manufacturer: Analog Devices

Specifications of AD7652

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 500kSPS
• Interface: Par,Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: Uni (Vref),Uni 2.5V
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

MASTER SERIAL INTERFACE
Internal Clock
The AD7652 is configured to generate and provide the serial
data clock SCLK when the EXT/ INT pin is held LOW. The
AD7652 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted if desired. Depending on the
RDC/SDIN input, the data can be read after each conversion or
during the following conversion. F
the detailed timing diagrams of these two modes.
CS, RD
CS, RD
SDOUT
CNVST
SDOUT
CNVST
BUSY
SYNC
SCLK
BUSY
SYNC
SCLK
t
16
t
3
Figure 33. Master Serial Data Timing for Reading (Read Previous Conversion during Convert
igure 32
t
t
t
14
15
16
t
t
t
14
15
29
t
17
X
t
t
Figure 32. Master Serial Data Timing for Reading (Read after Convert)
18
22
and
EXT/INT = 0
t
EXT/INT = 0
1
Figure 33
t
D15
3
X
t
t
1
20
22
t
19
t
21
t
20
D14
t
D15
2
23
show
1
t
19
t
18
Rev. 0 | Page 21 of 28
RDC/SDIN = 0
RDC/SDIN = 1
D14
t
2
t
21
3
23
t
28
3
Usually, because the AD7652 is used with a fast throughput,
Master Read During Conversion is the most recommended
serial mode. In this mode mode, the serial clock and data toggle
at appropriate instants, minimizing potential feedthrough
between digital activity and critical conversion decisions.
In Read After Conversion mode, it should be noted that unlike
in other modes, the BUSY signal returns LOW after the 16 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.
INVSCLK = INVSYNC = 0
14
D2
INVSCLK = INVSYNC = 0
14
D2
15
D1
15
D1
16
t
24
16
t
30
D0
t
D0
24
02964-0-015
02964-0-016
t
t
t
t
t
t
25
26
27
25
26
27
AD7652