AD7910 Analog Devices, AD7910 Datasheet - Page 18

• Manufacturer Part Number: AD7910
• Description: 250 kSPS, 10-Bit ADC in 6 Lead SC70
• Manufacturer: Analog Devices

Specifications of AD7910

• Resolution (bits): 10bit
• # Chan: 1
• Sample Rate: 250kSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni Vdd
• Adc Architecture: SAR
• Pkg Type: SC70,SOP

AD7910/AD7920
POWER VS. THROUGHPUT RATE
By using the power-down mode on the AD7910/AD7920 when
not converting, the average power consumption of the ADC
decreases at lower throughput rates. Figure 22 shows how, as the
throughput rate is reduced, the device remains in its power-
down state longer and the average power consumption over
time drops accordingly.
For example, if the AD7910/AD7920 is operated in a
continuous sampling mode with a throughput rate of 100 kSPS
and an SCLK of 5 MHz (V
the power-down mode between conversions, the power
consumption is calculated as follows.
The power dissipation during normal mode is 15 mW (V
The power dissipation includes the power dissipated while the part
is entering power-down mode, the power dissipated during the
dummy conversion (when the part is exiting power-down mode
and powering up), and the power dissipated during conversion.
As mentioned in the power-down mode section, to enter
power-down mode, CS has to be brought high anywhere
between the second and tenth SCLK falling edge. Therefore, the
power consumption when entering power-down mode varies
depending on the number of SCLK cycles used. In this example,
five SCLK cycles are used to enter power-down mode. This
gives a time period of 5 × (1/f
The power-up time is 1 μs, which implies that only five SCLK
cycles are required to power up the part. However, CS has to
remain low until at least the tenth SCLK falling edge when
exiting power-down mode. This means that a minimum of nine
SCLK cycles have to be used to exit power-down mode and
power up the part.
So, if nine SCLK cycles are used, the time to power up the part
and exit power-down mode is 9 × (1/f
Finally, the conversion time is 16 × (1/f
DD
= 5 V), and the device is placed in
SCLK
) = 1 μs.
SCLK
SCLK
) = 1.8 μs.
) = 3.2 μs.
DD
= 5 V).
Rev. C | Page 18 of 24
Therefore, the AD7910/AD7920 can be said to dissipate 15 mW
for 3.2 μs + 1.8 μs + 1 μs = 6 μs during each conversion cycle. If
the throughput rate is 100 kSPS, the cycle time is 10 μs and the
average power dissipated during each cycle is (6/10) × (15 mW)
= 9 mW. The power dissipation when the part is in power-down
has not been taken into account because the shutdown current
is so low and it does not have any effect on the overall power
dissipation value.
If V
down mode between conversions, the power dissipation during
normal operation is 4.2 mW. Assuming the same timing
conditions as before, the AD7910/AD7920 can now be said to
dissipate 4.2 mW for 6 μs during each conversion cycle. With a
throughput rate of 100 kSPS, the average power dissipated
during each cycle is (6/10) × (4.2 mW) = 2.52 mW. Figure 22
shows the power vs. throughput rate when using the power-
down mode between conversions with both 5 V and 3 V
supplies.
Power-down mode is intended for use with throughput rates of
approximately 160 kSPS and under because at higher sampling
rates there is no power saving made by using the power-down
mode.
DD
0.01
100
= 3 V, SCLK = 5 MHz, and the device is again in power-
0.1
10
1
0
20
Figure 22. Power vs. Throughput Rate
40
V
V
DD
DD
THROUGHPUT RATE (kSPS)
= 3V, SCLK = 5MHz
= 5V, SCLK = 5MHz
60
80
100
120
140
160
180