AD9874 Analog Devices, AD9874 Datasheet
AD9874
Specifications of AD9874
Available stocks
Related parts for AD9874
AD9874 Summary of contents
Page 1
... The AD9874 is a general-purpose IF subsystem that digitizes a low level 10 MHz to 300 MHz IF input with a signal bandwidth ranging from 6.8 kHz to 270 kHz. The signal chain of the AD9874 consists of a low noise amplifier, a mixer, a band-pass sigma-delta analog-to-digital converter, and a decimation filter with program- mable decimation factor ...
Page 2
... AD9874 TABLE OF CONTENTS AD9874—SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 3 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 5 PIN CONFIGURATION/DESCRIPTION . . . . . . . . . . . . . 6 DEFINITION OF SPECIFICATIONS/ TEST METHODS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 TYPICAL PERFORMANCE CHARACTERISTICS . . . . . 8 SERIAL PERIPHERAL INTERFACE (SPI SYNCHRONOUS SERIAL INTERFACE (SSI Synchronization Using SYNCB . . . . . . . . . . . . . . . . . . . . 18 Interfacing to DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 POWER CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 LO SYNTHESIZER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Fast Acquire Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CLOCK SYNTHESIZER . . . . . . . . . . . . . . . . . . . . . . . . . . 21 IF LNA/MIXER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 BAND-PASS SIGMA DELTA ( - ) ADC ...
Page 3
... AD9874–SPECIFICATIONS VDDQ = VDDP = 2 5 MSPS, f CLK Parameter SYSTEM DYNAMIC PERFORMANCE SSB Noise Figure @ Min VGA Attenuation Max VGA Attenuation 3, 4 Dynamic Range with AGC Enabled IF Input Clip Point @ Max VGA Attenuation 3 @ Min VGA Attenuation Input Third Order Intercept (IIP3) ...
Page 4
... AD9874 DIGITAL SPECIFICATIONS MSPS 109.65 MHz 107.4 MHz, f CLK IF LO Parameter DECIMATOR 2 Decimation Factor Pass-Band Width Pass-Band Gain Variation Alias Attenuation SPI-READ OPERATION (See Figure 1a) PC Clock Frequency PC Clock Period (t ) CLK PC Clock Clock LOW (t ) LOW Setup Time (t ...
Page 5
... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9874 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
Page 6
... Positive Power Supply for Internal Digital Function. PIN CONFIGURATION MXOP 1 36 PIN 1 MXON 2 IDENTIFIER 35 GNDF 3 34 IF2N 4 33 IF2P 5 32 AD9874 VDDF 6 31 TOP VIEW GCP 7 30 (Not to Scale) GCN 8 29 VDDA 9 28 GNDA 10 VREFP 11 26 VREFN ...
Page 7
... INTER characteristic of the component or system to degrade, thus making it unable to detect the smaller target signal correctly. In SNR ) the case of the AD9874 often a degradation in noise figure IN OUT at increased VGA attenuation settings that limits its dynamic range (refer to TPCs 15a, 15b, and 15c). ...
Page 8
... AD9874–Typical Performance Characteristics (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5 –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.) A 100 80 –40 C + 7.2 7.5 7.8 8.1 8.4 8.7 9.0 NOISE FIGURE – dB TPC 1a ...
Page 9
... DIGITAL INTERFACE 2 (IDDH – MHz CLK TPC 6b. Supply Current vs. f CLK 2 (VDDx = 3.0 V, High Bias ) –9– AD9874 = 109.56 MHz 107.4 MHz –17.5 –18.0 –18.5 +85 C –19.0 +25 C –19.5 –40 C –20.0 –20.5 2.7 3.0 3.3 VDDx – V TPC 4c. Maximum VGA Attenuation 3 Clip Point vs ...
Page 10
... AD9874 (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5 –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.) A 0.1 0 –0.1 LOW BIAS –0.2 HIGH BIAS –0.3 –0.4 –0.5 –0.6 – ...
Page 11
... IFIN – dBm TPC 12b. IMD vs. IFIN ( MSPS) CLK –11– AD9874 = 109.56 MHz 107.4 MHz 10.0 16-BIT DATA w/ DVGA ENABLED 9.5 24-BIT 16-BIT DATA DATA 9.0 8.5 8.0 7.5 ...
Page 12
... AD9874 (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5 –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted 16-BIT w/DVGA 24-BIT 100 150 200 250 300 350 400 450 500 FREQUENCY – ...
Page 13
... LOTM Manual Control of LO Charge Pump (0 = Off Up Down Normal). LOFA(13:8) LO Fast Acquire Time Unit (6 MSB of a 14-Bit Word). LOFA(7:0) LO Fast Acquire Time Unit (8 LSB of a 14-Bit Word). –13– AD9874 ( 16.8 MHz. REF = (LOI + 1) 0.625 mA. ...
Page 14
... AD9874 Address Bit (Hex) Breakdown Width Default Value CLOCK SYNTHESIZER 0x10 (5: 0x11 (7:0) 8 0x38 0x12 (4:0) 5 0x00 0x13 (7:0) 8 0x3C 0x14 ( ( (4: (1: 0x15 (5:0) 6 0x0 0x16 (7:0) 8 0x04 SSI CONTROL 0x18 (7:0) 8 0x12 0x19 (7:0) 8 0x07 0x1A (3: ADC TUNING 0x1C ( (0) ...
Page 15
... SERIAL PORT INTERFACE (SPI) The serial port of the AD9874 has 3-wire or 4-wire SPI capability, allowing read/write access to all registers that configure the device’s internal parameters. The default 3-wire serial commu- nication port consists of a clock (PC), peripheral enable (PE), and bidirectional data (PD) signal. The inputs to PC, PE, and PD contain a Schmitt trigger with a nominal hysteresis of 0 ...
Page 16
... The SSI control registers are SSICRA, SSICRB, and SSIORD. Table III shows the different bit fields associated with these registers. The primary output of the AD9874 is the converted I and Q demodulated signal available from the SSI port as a serial bit stream contained within a frame. The output frame rate is equal ...
Page 17
... AGC and status information (1) Figure 3b. Timing Parameters for SSI Timing* *Timing parameters also apply to inverted CLKOUT or FS modes, with t relative to the falling edge of the CLK and/or FS. –17– AD9874 RSSI0 ATTN7 ATTEN6 START I0 STOP BIT Q15 ...
Page 18
... Capacitive Load for Each DS Setting Synchronization Using SYNCB Many applications require the ability to synchronize one or more AD9874 in a way that causes the output data to be precisely aligned to an external asynchronous signal. For example, receiver applications employing diversity often require synchronization of multiple AD9874 digital outputs ...
Page 19
... Wake-up time is dependent on programming and/or external components. REV. A The AD9874 also allows control over the bias current in the LNA, ADSP-2153x mixer, and clock oscillator. The effects on current consumption and system performance are described in the section dealing SPI-PORT with the affected block ...
Page 20
... Also, a free software copy of the Analog Devices ADIsimPLL, a PLL synthesizer simulation tool, is available at www.analog.com. Note that the ADF4112 model can be used as a close approxima- tion to the AD9874’s LO synthesizer when using this software tool. LOP LO BUFFER LON FREF ...
Page 21
... I setting, while Figure 7c shows that the higher charge pump values provide the optimum performance for the given loop filter configuration. The AD9874 clock synthesizer and oscilla- tor were set up to provide 16.8 MHz. The following external component values VDDC = 3 ...
Page 22
... MHz. Figures 9a and 9b show the equivalent input impedance versus frequency characteristics of the AD9874 with all the LNA bias settings. The increase in shunt resistance versus frequency can be attributed to the reduction in bandwidth, thus the amount of negative feedback of the LNA. ...
Page 23
... AD9874’s on-chip programmable capacitor array. Since the programming range of the capacitor array is at least 160 pF, the AD9874 has plenty of range to make up for the tolerances of low cost external components. Note that increased by a factor of 1.44 MHz to 26 MHz so that f becomes 3.25 MHz, reducing L and C by approximately the same factor (i.e 6.9 µ ...
Page 24
... BAND-PASS SIGMA-DELTA ( - ) ADC The ADC of the AD9874 is shown in Figure 12. The ADC contains a sixth order multibit band-pass - modulator that achieves very high instantaneous dynamic range over a narrow frequency band. The loop filter of the band-pass - modulator consists of two continuous-time resonators followed by a discrete- time resonator, with each resonator stage contributing a pair of complex poles ...
Page 25
... CLK either automatically or manually via the SPI port. The capaci- tors of the active RC resonator are similarly programmable. Note that the AD9874 can be placed in and out of its standby mode without retuning since the tuning codes are stored in the SPI Registers. When tuning the LC tank, the sampling clock frequency must be stable and the LNA/mixer, LO synthesizer, and ADC must all be placed in standby ...
Page 26
... AD9874 Once the AD9874 has been tuned, the noise figure degradation attributed solely to the temperature drift of the LC and RC resonators is minimal. Since the drift of the RC resonator is actually negligible compared to that of the LC resonator, the external L and C components’ temperature drift characteristics tend to dominate. Figure 13d shows the degradation in noise figure as the product of the LC value is allowed to vary from – ...
Page 27
... NORMALIZED FREQUENCY – RELATIVE TO Figure 17a. Folded Decimator Frequency Response for –20 –40 0.250 f OUT –60 –80 MIN ALIAS ATTN = 97.2dB –100 –120 0 NORMALIZED FREQUENCY – RELATIVE TO Figure 17b. Folded Decimator Frequency Response for 0.250 f OUT –27– AD9874 0.50 0.25 f OUT 0.50 0.25 f OUT ...
Page 28
... VDDI and VDDF as the VGA changes from attenuation. The purpose of the VGA is to extend the usable dynamic range of the AD9874 by allowing the ADC to digitize a desired signal over a large input power range as well as recover a low level signal in the presence of larger unfiltered interferers without saturating or clipping the ADC ...
Page 29
... ADC reset occurrences within the final I/Q update rate of the /60 and can be CLK AD9874, as well as the AGC value (8 MSB), can be read from the SSI data upon proper configuration. The AGC performs digital signal estimation at the output of the first decimation stage (DEC1) as well as the DVGA output that follows the last decimation stage (DEC3) ...
Page 30
... AD9874 the maximum bandwidth is 9 kHz. A general expression for the attack bandwidth is: × × MHz 2 A CLK and the corresponding attack time is: ( AGCA 2 = × π × 100 . 2 attack assuming that the loop dynamics are essentially those of a single-pole system ...
Page 31
... As Figure 22a shows, the AD9874 can achieve an SNR in excess of 100 dB in narrow-band applications. To realize the full performance of the AD9874 in such applications recom- mended that the I/Q data be represented with 24 bits. If 16-bit data is used, the effective system NF will increase because of the quantization noise present in the 16-bit data after truncation ...
Page 32
... SNR performance. The major sources of spurs in the AD9874 are the ADC clock and digital circuitry operating at 1 CLK important variable in determining which LO (and therefore IF) frequencies are viable ...
Page 33
... This data indicates that the AD9874 does an excellent job of preserving the purity of the LO signal. Figure 25 can also be used to gauge how well the AD9874 rejects undesired signals. For example, the half-IF response (at 69.975 MHz and 72.225 MHz) is approximately –100 dBFS, giving a selectivity for this spurious response. The largest spurious response at approximately – ...
Page 34
... IF filtering requirements and eliminates the need for an external AGC. Figure 27 shows a typical dual conversion superheterodyne receiver using the AD9874 tuner is used to select and downconvert the target signal to a suitable first IF for the AD9874. A preselect filter may precede the tuner to limit the RF input to the band of interest ...
Page 35
... I and Q components, filtered via matching decimation filters, and reformatted to enable a synchronous serial interface to a DSP. In this example, the AD9874’s LO and CLK synthesizers are both enabled, requiring some additional passive components (for the synthesizer’s loop filters and CLK oscillator) and a VCO for the LO synthesizer ...
Page 36
... SPI register con- figuration since they share the same SPI interface to the DSP. Since the state of each of the AD9874’s internal counters is unknown upon initialization, synchronization of the devices is required via a SYNCB pulse (see Figure 4) to synchronize their digital filters and ensure precise time alignment of the data streams ...
Page 37
... This configuration results in the best possible receiver sensitivity under all blocking conditions. The output of the last SAW filters drives the two AD9874s via a direct signal path and an attenuated signal path. The direct path corresponds to the AD9874 having the lowest clip point and provides the highest receiver sensitivity with a system noise figure of 4 ...
Page 38
... The AD9874 can be operated in the hung mixer mode by tying one of the LO’s self-biasing inputs to ground (i.e., GNDI) or the positive supply (VDDI). In this mode, the AD9874 acts as a narrow-band, band-pass - ADC, since its mixer passes the IFIN signal without any frequency translation. The IFIN signal must be centered about the resonant frequency of the - ADC (i ...
Page 39
... REV. A OUTLINE DIMENSIONS 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 1.60 MAX PIN 1 INDICATOR 0.75 0.60 0.45 SEATING PLANE 0.20 0.09 VIEW 0.08 MAX COPLANARITY 0.50 VIEW A BSC COMPLIANT TO JEDEC STANDARDS MS-026BBC –39– AD9874 9.00 BSC TOP VIEW 7.00 BSC (PINS DOWN 0.27 0.22 0.17 ...
Page 40
... AD9874 Revision History Location 3/03—Data sheet changed from REV REV. A Change to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Replaced Figure Deleted Synchronization section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Added Synchronization Using SYNCB section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Changes to LO SYNTHESIZER section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Changes to Figure Changes to Figure Changes to Table X ...